TLE5012B
SSC Registers
User’s Manual 80 Rev. 1.2, 2018-02
AS_DSPU 4 wu Activation DSPU BIST
0
B
after execution
1
B
activation of DSPU BIST or BIST running
Reset: 1
B
(for update buffer 0
B
if no update command
send before)
AS_FUSE 3 wu Activation Fuse CRC
A write in any of the fuse registers will set this bit
automatically (automatically enabled by deactivation of
AUTOCAL). AUTOCAL disables register CRC check
regardless of the AS_FUSE setting.
0
B
monitoring of CRC disabled. Clearing this
activation bit will also disable reporting of S_FUSE
errors after a remaining error has been read-out.
1
B
monitoring of CRC enabled
Reset: 1
B
(for update buffer 0
B
if no update command
send before)
AS_VR 2 wu Enable Voltage Regulator Check
0
B
check of regulator voltages disabled. Clearing this
activation bit will also disable reporting of S_VR
error after a remaining error has been read-out.
1
B
check of regulator voltages enabled
Reset: 1
B
(for update buffer 0
B
if no update command
send before)
AS_WD 1 wu Enable DSPU Watchdog
0
B
DSPU watchdog monitoring disabled. The S_WD
status will be immediately cleared, when this bit is
cleared.
1
B
DSPU Watchdog monitoring enabled.
Reset: 1
B
(for update buffer 0
B
if no update command
send before)
AS_RST 0 w Activation of Hardware Reset
Activation occurs after CSQ switches from ’0’ to ’1’ after
SSC transfer.
0
B
after execution (write only, thus always returns “0”).
1
B
activation of HW Reset (S_RST is set).
Reset: 0
B
1) existing error may remain in STAT register even after SSC read-out due to asynchronity between SSC write of AC_STAT
register and internal firmware execution. Thus this activation bit should only be cleared during start-up.
Field Bits Type Description
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