TLE5012B
SSC Registers
User’s Manual 92 Rev. 1.2, 2018-02
Synchronicity Register
SYNCH Offset Reset Value
Synchronicity 0C
H
device-specific
Field Bits Type Description
SYNCH 15:4 w Amplitude Synchronicity
12-bit signed integer value of amplitude synchronicity
correction (raw X amplitude divided by raw Y amplitude).
For synchronicity correction, the offset compensated Y
value is multiplied by SYNCH.
+2047
D
112.494%
0
D
100%
-2048
D
87.500%
Reset: device-specific
15 8
7 0
15
w
SYNCH
74
w
SYNCH
30
Res
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