171
II - PIN DESCRIPTION
(continued)
Pin Name Type Function
SDRAM INTERFACE
78-81, 69, 70-74, 82, 83 AD[0:11] O SDRAM Address Bus
92-94, 97-101, 106-109,
112-115
DQ[0:15] I/O SDRAM Data (Lower Byte)
84, 85
SDCS[0:1] O SDRAM Chip Selects
89
SDCAS O SDRAM CAS
88
SDRAS O SDRAM RAS
90
SDWE O SDRAM Write Enable
104 MEMCLKIN I SDRAM Memory Clock Input
76 MEMCLKOUT O SDRAM Memory Clock Output
91 DQML O DQ Mask Enable (Lower)
105 DQMU O DQ Mask Enable (Upper)
EXTERNAL MEMORY INTERFACE
161-170, 173-183 ADR[1:21] I/O External Memory Address Bus
141-148, 151-158 DATA[0:15] I/O External Memory Data Bus
128
RAS1/HOLDREQ O DRAM RAS or reserved
136 WAIT/READY I/O External Wait States or Reserved
133 R/
W/DMAACK I/O DRAM R/W Strobe or Reserved
121, 122
BE[0:1] O Byte enable
129
CAS0/HOLDACK O/I DRAM CAS or Reserved
132
CAS1/DMAREQ O DRAM CAS or Reserved
124-126
CE[1:3] O Chip Select for Banks 1 - 3
135
CS I Reserved
137 PROCCLK I/O ST20 Clock or Reserved
127
RAS0/CE0 O DRAM RAS or Chip Select for Bank 0
134 DMAXFER I Reserved
138
PPC_MODE I Reserved
123
OE I/O Output Enable or Reserved
SDAV/P1394 INTERFACE
30 TEST1 I/O DATA_RX/STROBE_TX (SDAV Mode) or SDAV_CLK
(P1394 Mode)
31 TEST2 I/O STROBE_RX/DATA_TX (SDAV Mode) or
DATA_IN/DATA_OUT (P1394 Mode)
32 TEST3 I/O Direction (SDAV Mode) or DATA_VALID In/Out (P1394
Mode)
MISCELLANEOUS
41 TEST5 O NRSS_OUT (DVB/DSS)
II.2 - Pin List
(continued)
STi5505 (Rev. Ax)