Marantz SA12 - General-Purpose In;Outputs

177
RESETn is an asynchronous reset and should be low for at
least 1 period of DSD_CLK.
General-purpose in/outputs.
Four general purpose input and output signals are available.
9.24.6 Pin description
IC-Pin_no Name Type Function
1 H_DQ[13] I/O5 Data bus
2 H_DQ[12] I/O5 Data bus
3 VCC_IO IN 3.3V power supply IO
4 GND_IO IN Ground
5 H_DQ[11] I/O5 Data bus
6 H_DQ[10] I/O5 Data bus
7 H_DQ[9] I/O5 Data bus
8 H_DQ[8] I/O5 Data bus
9 H_DQ[7] I/O5 Data bus
10 H_DQ[6] I/O5 Data bus
11 H_DQ[5] I/O5 Data bus
12 H_DQ[4] I/O5 Data bus
13 VCC_CORE IN 3.3V power supply Core
14 GND_CORE IN Ground(core)
15 H_DQ[3] I/O5 Data bus
16 H_DQ[2] I/O5 Data bus
17 H_DQ[1] I/O5 Data bus
18 H_DQ[0] I/O5 Data bus
19 VCC_IO IN 3.3V power supply IO
20 H_procclock IN Host processor EMI interface clock
21 GND_IO IN Ground
22 H_WAIT O5 Wait signal
23 H_RWn IN READ=1,Write=0
24 H_CSLn IN Chip Select, active low
25 H_CSHn IN Chip select
26 H_ben(1) IN Byte Enable 1
27 H_ben(0) IN Byte Enable 0
28 B_V4 IN Versatile Input Pin (contains Subcode), not used
29 B_SYNC IN Sector sync / Absolute time sync
30 B_FLAG IN I2S flag (EDC flag)
31 B_BCLK IN I2S Bit ClocK
32 B_WCLK IN I2S Word CLock
33 B_DATA IN I2S Data
34 GP_in_pin(0) IN General purpose in
35 GP_in_pin(1) IN General purpose in
36 AD[6] I/O5
37 AD[5] I/O5
38 AD[4] I/O5
39 VCC_CORE IN 3.3V power supply Core
40 GND_CORE IN Ground(core)
41 AD[3] I/O5
42 AD[2] I/O5
43 AD[1] I/O5
44 AD[0] I/O5 Digital out of AD OR digital in for PLL
45 GP_in_pin (2) IN General purpose in
46 biasin APIO Current input. connect via 15K to VSS
47 vddaagc VDDCO VDD of AGC ( + 3.3V)
48 Agcadctstp APIO AGC Positive channel test pin
49 vssaagc VSSCO Analog ground for AGC.
50 agcinp APIO AGC positive input signal, HF in.
51 VCC_IO IN 3.3V power supply IO
52 GND_IO In Ground
53 agcadctstn APIO AGC Negative channel test pin
54 vssaadc VSSCO VSS of AGC & ADC connected to substrate
55 vddaadc VDDCO VDD of ADC ( +3.3V)
56 adcrefh APIO ADC decoupling high . (via 100nF to VSS)
57 Adcrefm APIO ADC decoupling middle . (via 100nF to VSS)