Marantz SA12 - Page 136

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58 adcrefl APIO ADC decoupling low. (via 100nF to VSS)
59 vssrefadc VSSCO VSS of Reference Ladder of ADC ( not to the substrate)
60 PCM_LeRi_in IN PCM data Left/Right
61 PCM_CeLf_in IN PCM data Centre/LFE
62 PCM_LsRs_in IN PCM data lift/Right surround
63 PCM_wclk_in IN PCM word clock
64 PCM_dclk_in IN PCM data clock
65 VCC_CORE IN 3.3V power supply Core
66 GND_CORE IN Ground(core)
67 GP_in_pin (3) IN General purpose in
68 D_ADDR[4] O5 SDRAM Address bus
69 D_ADDR[5] O5 SDRAM Address bus
70 GND_IO IN Ground
71 D_ADDR[6] O5 SDRAM Address bus
72 D_ADDR[7] O5 SDRAM Address bus
73 D_ADDR[8] O5 SDRAM Address bus
74 D_ADDR[9] O5 SDRAM Address bus
75 VCC_IO IN 3.3V power supply IO
76 D_clk O5 Clock signal needed for SDRAM.
77 GND_IO IN Ground
78 D_ADDR[0] O5 SDRAM Address bus
79 D_ADDR[1] O5 SDRAM Address bus
80 D_ADDR[2] O5 SDRAM Address bus
81 D_ADDR[3] O5 SDRAM Address bus
82 VCC_IO IN 3.3V power supply IO
83 GND_IO IN Ground
84 D_ADDR[10] O5 SDRAM Address bus
85 D_ADDR[11] O5 SDRAM Address bus
86 GND_IO - Ground.
87 D_RASn O5 Row Address Select
88 D_CASn O5 Column Address Select
89 D_Wen O5 Read/Write
90 D_LDQM O5 DQ mask enable (lower)
91 VCC_CORE IN 3.3V power supply Core
92 GND_CORE IN Ground(core)
93 D_UDQM O5 DQ mask enable (Upper)
94 D_DQ[0] I/O5 Data bus
95 VCC_IO IN 3.3V power supply IO
96 D_DQ[1] I/O5 Data bus
97 D_DQ[2] I/O5 Data bus
98 D_DQ[3] I/O5 Data bus
99 D_DQ[4] I/O5 Data bus
100 VCC_IO IN 3.3V power supply IO
101 GND_IO IN Ground
102 D_DQ[5] I/O5 Data bus
103 D_DQ[6] I/O5 Data bus
104 D_DQ[7] I/O5 Data bus
105 D_DQ[8] I/O5 Data bus
106 D_DQ[9] I/O5 Data bus
107 D_DQ[10] I/O5 Data bus
108 D_DQ[11] I/O5 Data bus
109 D_DQ[12] I/O5 Data bus
110 VCC_IO IN 3.3V power supply IO
111 GND_IO IN Ground
112 D_DQ[13] I/O5 Data bus
113 D_DQ[14] I/O5 Data bus
114 D_DQ[15] I/O5 Data bus
115 D_ADDR[12] O5 SDRAM Address bus
116 D_ADDR[13] O5 SDRAM Address bus
117 VCC_CORE IN 3.3V power supply Core
118 GND_CORE IN Ground(core)
IC-Pin_no Name Type Function