Matrox Solios Series - Page 14

14 Chapter 1: Introduction
Matrox Solios eCL/XCL-F
Matrox Solios eCL/XCL-F supports acquisition from one Camera Link device in
the Base, Medium, or Full configuration (with up to 10 taps). Matrox Solios
eCL/XCL-F supports Camera Link frequencies of up to 85 MHz; additionally,
Matrox Solios eCL/XCL-F supports the Processing FPGA option.
PSG
First
MDR-26
connector
ChannelLink
Receiver #1
Clock
Data (24)
& Syncs (4) *
Second
MDR-26
connector
UART
LVDS
drivers
and
receivers
OptoAux (4)
DB-44 and
DB-9
connectors**
TTL buffers
** On a separate bracket.
Aux In (4)
Aux Out (2)
HSYNC Out (1)
VSYNC Out (1)
Clock Out (1)
Optocoupler
Aux I/Os (4)
ChannelLink
Receiver #2
Clock
Data (28) *
Cam Ctrl (4)
LVDS
drivers
LVDS driver
& receiver
16
64 DDR
(up to 1.76 GB/s)
64
(up to 880 MB/s)
PCI-X to PCIe Bridge
64-bit (up to 1 GB/s)
28
24
LUTs
Demultiplexer
Matrox Solios eCL/XCL-F
Acquisition
memory
(64/128/256 MB)
16
Optional
(up to
924 MB/s)
(up to
924 MB/s)
32
(up to 0.67 GB/s)
32
(up to 0.67 GB/s)
Video to
PCI-X
bridge
Color
space
ChannelLink
Receiver #3
Clock
Data (28) *
28
64
* 28 bits serialized across 4 LVDS pairs.
Host PCI / PCI-X / PCIe bus
SerTC
SerTFG
QDRII
SRAM
(4/8MB)
Processing
FPGA
64
(up to 1.3 GB/s)
DDR SDRAM
(64/128/256 MB)
5V/3.3V PCI/PCI-X (XCL)x4 PCIe (eCL)
(Up to 1 GB/s)