Matrox Solios Series - Page 13

Matrox Solios boards 13
PSG
First
MDR-26
connector
ChannelLink
Receiver #1
Clock
Data (24)
& Syncs (4)*
SerTFG
SerTC
Second
MDR-26
connector
24
UART
LVDS
drivers
and
receivers
OptoAux (4)
DB-44 and
DB-9
connectors**
TTL buffers
On a separate bracket.
Aux In (4)
Aux Out (2)
HSYNC Out (1)
VSYNC Out (1)
Clock Out (1)
Optocoupler
Aux I/Os (4)
ChannelLink
Receiver #2
Clock
Data (24)
& Syncs (4)*
24
Cam Ctrl (4)
LVDS
drivers
LVDS driver
& receiver
16
64 DDR
(up to 1.6 GB/s)***
64
(up to 800 MB/s)****
PCI-X to PCI-X (XCL)
or PCI-X to PCIe (eCL)
Bridge
Host PCI/PCI-X/PCIe bus
LUTs
48
Demultiplexer
Matrox Solios eCL/XCL
dual-Base/single-Medium
(single-Medium mode)
Acquisition
memory
(64/128/256 MB)
16
Processing
FPGA
DDR SDRAM
(64/128/256 MB)
64
(up to 1.3 GB/s)
QDRII
SRAM
(4/8 MB)
Optional
28 bits serialized across 4 LVDS pairs.
(up to
924 MB/s)
(up to
924 MB/s)
32
(up to 0.67 GB/s)
32
(up to 0.67 GB/s)
Up to 1.6 GB/s for fast Camera Link board or with optional
Processing FPGA installed, otherwise up to 1.32 GB/s.
Up to 800 MB/s
optional Processin
g
FPGA installed, otherwise up to 660 MB/s.
for fast Camera Link board or with
Video to
PCI-X
bridge
Color
space
converter
*
**
***
****
5V/3.3V PCI/PCI-X (XCL)
64-bit (up to 1 GB/s)
x4 PCIe (eCL)
(Up to 1 GB/s)