Matrox Solios Series - Page 56

56 Chapter 4: Matrox Solios hardware reference
24
24
PSG
First
MDR-26
connector
ChannelLink
Receiver #1
Clock
Data (24)
& Syncs (4)*
SerTFG
SerTC
Second
MDR-26
connector
UART
LVDS
drivers
and
receivers
OptoAux (4)
DB-44 and
DB-9
connectors**
TTL buffers
Aux In (4)
Aux Out (2)
HSYNC Out (1)
VSYNC Out (1)
Clock Out (1)
Optocoupler
Aux I/Os (4)
ChannelLink
Receiver #2
Clock
Data (24)
& Syncs (4)*
Cam Ctrl (4)
LVDS
drivers
LVDS driver
& receiver
LUTs
48
Demultiplexer
* 28 bits serialized across 4 LVDS pairs.
Video
to
PCI-X
bridge
Acquisition section of
Matrox Solios eCL/XCL
dual-Base/single-Medium
(single-Medium mode)