Matrox Solios Series - Page 55

Matrox Solios eCL/XCL acquisition section 55
PSG #0
PSG #1
First
MDR-26
connector
ChannelLink
Receiver #1
Clock
Data (24)
& Syncs (4)*
SerTFG
SerTC
SerTFG
SerTC
Second
MDR-26
connector
24
UART
UART
LVDS
drivers
and
receivers
OptoAux (4)
DB-44 and
DB-9
connectors**
TTL buffers
Aux In (4)
Aux Out (4)
HSYNC Out (2)
VSYNC Out (2)
Clock Out (2)
Optocoupler
Aux I/Os (6)
ChannelLink
Receiver #2
Clock
Data (24)
& Syncs (4)*
24
LUTs
LUTs
32
32
Cam Ctrl (4)
Cam Ctrl (4)
LVDS
drivers
LVDS
drivers
LVDS driver
& receiver
LVDS driver
& receiver
Video
to
PCI-X
Bridge
Demultiplexer
Demultiplexer
Acquisition section of
Matrox Solios eCL/XCL
dual-Base/single-Medium
(dual-Base mode)
** On a separate bracket.
* 28 bits serialized across 4 LVDS pairs.