Minebea CSD-581-15 - 7−2−6. Output Condition; 7−2−7. Selection of Output Logic for P.C.(Print Command), and Its Width

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 ● P.C. output transistor will be OFF (Positive logic electrically) at the
time of HOLD signal input. However, as for P.C., it will be OFF
condition after one shot of operation is over.
● After inputting HOLD signal, the following response times will be
required until DATA and POL. are frozen or HOLD is cancelled.
At 50 times/s：Approx.120 ms at max.
At 20 times/s：Approx. 150 ms at max.
At 4 times/s：Approx. 350 ms at max.
7−2−6. Output condition
Setting
output
logic
Output
data
Transisto
r
Pin−COM level
when
voltage
is
S
ett
i
ng output
l
og
i
c
O
utput
d
ata
Transistor
condition
w
h
en vo
l
tage
i
s
supplied externally.
Negative
logic
Ye s ON L
N
egat
i
ve
l
og
i
c
No OFF H
P
ositive
logic
Ye s OFF H
P
os
i
t
i
ve
l
og
i
c
No ON L
7−2−7. Selection of output logic for P.C.(Print command), and its width
The selection of P.C. logic, width for the instrument can be performed with the DIP201 “DIP SW
for the setting of P.C. output” on the P.C. board. (Refer to the below figure.)
UP↑
Down↓
ON
OFF
Enlarged Fig.
CN202
DIP202
DIP203