2-4 MTR3000 Receiver Module: Functional Theory of Operation
2.3.1.2 Receiver Back End Circuitry
The signal after the image filter is then mixed down to the first IF, via a high performance (high IIP3)
mixer, driven by the low-phase noise, voltage-controlled Colpitts oscillator (VCO). The mixed-down
signal then passes through a 3-pole, crystal IF bandpass filter and an IF amplifier. The amplifier
output signal passes through another 3-pole crystal bandpass filter, and the resultant signal passes
through a digital step attenuator. The desired signal is then applied to the RF input of the backend
Receiver-specific IC.
2.3.1.3 Voltage Controlled Oscillator (VCO)
The Receiver Voltage Controlled Oscillator (VCO) generates a sinusoidal output signal that ranges
from 476.35 MHz to 543.35 MHz (UHF R1), 523.35 MHz to 597.35 MHz (UHF R2), 732.65 MHz to
751.65 MHz (800 MHz) and 969.35 MHz to 975.35 MHz (900 MHz). Either UHF R1, UHF R2, 800
MHz or 900 MHz can be used at a time. The Receive Voltage-Controlled Oscillator (RXVCO) line-up
consists of four sub-circuits: a Voltage-Controlled Oscillator (VCO), an attenuator, a buffer-amplifier,
and a low pass filter (LPF).
The active device is from oscillator topology, utilizing a high-Q resonator, and four anti-parallel-
configured, hyper-abrupt, tuning varactors.
The attenuator provides a broadband RF load for the VCO. The buffer-amplifier provides power-
leveling and isolation. The LPF provides VCO harmonic attenuation.
2.3.1.4 Synthesizer Circuitry
The Receiver synthesizer is a subcircuit within the receiver-specific IC, which when connected with a
loop filter, VCO, buffer amplifier, lowpass filter, driver amplifier, unequal splitter, and feedback
attenuator forms a phase-locked loop. The frequency and phase of the VCO is locked to a highly-
stable external Temperature Compensated Crystal Oscillator (TCXO) reference (16.8 MHz). This IC
contains the following integrated Phase locked loop (PLL) components: prescaler, fractional-N
divider, reference divider, phase detector, and charge-pump (for the external loop-filter). The
reference divider frequency is selected to be either 8.4 MHz, 5.6 MHz or 16.8 MHz (800/900 MHz
band).
2.3.1.5 Backend Receiver-specific IC Circuitry
The backend Receiver-specific IC provides additional amplification, filtering, and a second down-
conversion. The second IF signal is converted to a digital signal, and output via either a differential or
single-ended driver to the digital signal processor (DSP) in the SCM.
2.3.1.6 Memory Circuitry
The memory circuitry consists of an Electrically Erasable Programmable Read-Only Memory
(EEPROM), located in the Receiver. The SCM performs memory read and write operations via the
SPI bus. The Rx Front-End Filter tuning calibration is stored in the EEPROM. Therefore, no field
tuning is ever required for the Receiver.
2.3.1.7 Analog to Digital (ADC) Converter Metering Circuitry
Analog signals from points throughout the Receiver are applied to the ADC converter. These analog
signals are converted to digital signals and then sent to the SCM, via the Serial Peripheral Interface
(SPI) lines, upon request of the SCM.
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