MTR3000 Station Control Module: Functional Theory of Operation 5-3
5.2.1.1 External Memory
Both transmit and receive DSP’s support independent external memory banks.
5.2.1.1.1 RAM
The SCM supports Mobile Double Data Rate SDRAM. It has the following basic characteristics:
• 32 MB organized as 4 Mb x 16 x 4 Banks
• Four internal banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8 bytes
• Auto refresh and self refresh modes
• Selectable output drive (DS)
• VDD/VDDQ = 1.7–1.95 V
The maximum external clock rate for the DDR is 90 MHz. Since data is transferred on both clock
edges, the effective data rate is 180 Mwords/s.
5.2.1.1.2 Flash
The SCM supports 256 MB external flash memory. The device has the following basic
characteristics:
• Four 32 KBytes Bottom Boot Sectors
• 128 KBytes main blocks (254 for 256 Mbit part, 514 for 512 MBit part)
• 1.8V VCC and VCCO
5.2.1.2 Serial Peripheral Interface (SPI)
The station local and Intermodule SPI Bus is controlled by both Tx and Rx OMAP1710 processors,
which has an on-chip SPIF (fast SPI) interface. The OMAP1710 SPIF supports master and slave
modes, programmable clock rate, phase, polarity, programmable word size, programmable bit
ordering, and loopback.
Before an SPI data transfer can take place, the SPI master (initiator) must assert the select line of
the slave (target) device. The OMAP1710 is always the SPI master for base station/repeater. To
simplify overall SPI architecture for base station/repeater, address decoding is used instead of
individual device chip signals. This approach not only minimizes the number of GPIOs needed for
device chip select, it also provides flexibility for future expansion. This device address decoding is
handled by an Field Programmable Gate Array (FPGA) on the SCM and a Customer Programmable
Logic Device (CPLD) on each FRU’s, except the Power Supply.
The FPGA SPI module performs address and chip select decoding, level shifting, and signal mixing
for both the Tx OMAP SPI bus and the Rx OMAP SPI bus. Simultaneous Rx and Tx SPI accesses
are allowed. The Tx and Rx SPI are 100% independent.
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