Chapter 3
i.MX8 layout/routing recommendations
3.1 Introduction
This chapter provides recommendations to assist design engineers with the layout of an i.MX8 QM and i.MX8 QXP-based system.
3.2 Basic design recommendations
When using the Allegro design tool, it is recommended to use the schematic symbol and PCB footprint created by NXP. When
not using the Allegro tool, use the Allegro footprint export feature (supported by many tools). If the export is not possible, create
the footprint per the package dimensions outlined in the product data sheet.
The native Allegro layout and gerber files are available on www.nxp.com.
3.2.1 Placing decoupling capacitors
Place small decoupling and larger bulk capacitors on the bottom side of the PCB.
The 0201 or 0402 decoupling and 0603 (or larger) bulk capacitors should be mounted as close as possible to the power vias. The
distance should be less than 50 mils. Additional bulk capacitors can be placed near the edge of the BGA via array. Placing the
decoupling capacitors close to the power balls is critical to minimize inductance and ensure high-speed transient current required
by the processor. See the i.MX8 QM and i.MX8 QXP development platform layouts for examples of the desired decoupling
capacitor placement.
Correct via size is critical for preserving adequate routing space. The recommended geometry for the via and pads on an i.MX8
QM design is a metric 45r20 via (0.2 mm drill, 0.45 mm annular ring), while for an i.MX8 QXP design, it is an imperial 18r10 via
(10 mil drill, 18 mil annular ring). An 18r8 via may also be used.
The following list provides the main recommendations for choosing the correct decoupling scheme:
• Place the largest capacitance in the smallest package that the budget and manufacturing can support.
• For high-speed bypassing, select the required capacitance with the smallest package (for example, 0.1 μF, 0.22 μF, 1.0
μF, 2.2 μF, or even 4.7 μF in an 0201 package size).
• Minimize the trace length (inductance) to small caps.
• Series inductance cancels out capacitance.
• Tie caps to GND plane directly with a via.
• Place capacitors close to the power ball of the associated package from the schematic.
• A preferred BGA power decoupling design is available on the development platform board design available on
www.nxp.com. Customers should use the NXP design strategy for power and decoupling.
Note: NXP uses 0402 capacitors in its customer designs as an example for customers who may
not be able to use 0201 components. Nevertheless, NXP recommends using 0201 capacitor where
possible: 0201 capacitors have less package inductance and the number of capacitors placed
underneath the processor can be increased.
3.3 Stack-up recommendations
NXP Semiconductors
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
User's Guide 19 / 89
To Next Page
Loading...