• Preplanning impedance of critical traces is required.
• High-speed signals must have reference planes on adjacent layers to minimize crosstalk.
• Use PCB materials that have good transmission qualities at high frequencies utilized by the i.MX8 QXP interfaces. The
NXP i.MX8 QXP customer platform utilizes TU-872SLK Sp.
Figure 2. i.MX8 QXP board stack-up
3.4 DDR layout routing recommendations
3.4.1 DDR pin naming
The i.MX8 QXP processor can be used with either the LPDDR4 memory or the DDR3L memory. The iMX8 QM processor can be
used with the LPDDR4 memory. Because these memory types have different I/O signals, there are 33 generically named balls
that have different functions, depending on the type of memory used. See Table 16 for the connectivity of these generic balls for
DDR3L (QXP only) and LPDDR4 (QXP and 8QM). This table is for both processors, and the two columns shown in the “QM Ball
#” field are the ball numbers for channel 0 and channel 1 balls, respectively.
Table 16. DDR3L/LPDDR4 connectivity
Ball Name QXP Ball # QM Ball #
DDR3L
function (QXP)
LPDDR4 function
(QM, QXP)
DDR_DCF00 W1 U47 U7 A5 CA2_A
Table continues on the next page...
NXP Semiconductors
i.MX8 layout/routing recommendations
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
User's Guide 21 / 89
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