NXP strongly recommends that one of the example layouts provided for the i.MX8 designs be copied exactly for the placement
of the processor, DRAM device, decoupling capacitors underneath the processor, and the interconnecting traces/vias between
these parts. This includes the board stack-up design and PCB dielectric materials chosen. These designs have been tested and
validated at NXP and they are proven reliable. While NXP does not expect every customer to copy our designs, customers must
expect that the amount of support that can be provided for assisting a new design cannot be as great as the support provided for
designs already known to NXP.
NXP provides the processor IBIS models and timing models necessary for performing complete DRAM simulations of a design.
NXP strongly recommends that the end users perform simulations of any new designs before the release of a PCB layout design
for manufacturing.
Processor reference manuals and user’s guides are continuously reviewed and revised to contain the most up-to-date information
regarding the processor. In addition, erratas and engineering bulletins may be issued to document unintended processor behavior.
The design engineers should consult the official NXP website for the latest versions of these documents as a part of the final
checks of a PCB design before releasing the board to manufacturing.
When a fully assembled board is returned to the design engineer, it is the engineer’s responsibility to perform a complete check
of the board design to ensure that all subsystems are functioning correctly. See Thermal considerations for recommended board
bring-up guidelines.
3.7 Trace impedance recommendations
Use Table 26 as a reference when you are updating or creating constraints in the PCB design tool to set up the impedances/
trace widths.
Table 26. Trace impedance recommendations
Signal Group Impedance
PCB Manufacturer
Tolerance (+/-)
LPDDR4 signals (other than differentials)
42 Ω Single-ended (QXP)
10 %
42-44 Ω Single-ended (QM)
All user-critical signals, unless specified 50 Ω Single-ended 10 %
DDR (QM), PCIe transmit/receive data pairs 85 Ω differential 10 %
DDR (QXP), USB differential signals 90 Ω differential 10 %
Differential signals, including Ethernet, PCIe clocks, LVDS,
MIPI (CSI and DSI), SATA
100 Ω differential 10 %
Figure 17 shows the dimensions of a strip line and microstrip pair. Figure 18 shows the differential pair routing. Note the following:
• The space between two adjacent differential pairs should be greater than or equal to twice the space between the two
individual conductors.
• The skew between LVDS pairs should be within the minimum recommendation (± 100 mil).
NXP Semiconductors
i.MX8 layout/routing recommendations
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
User's Guide 51 / 89
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