Figure 29. USB connectivity on i.MX8QXP/8QM
If USB3 is to be supported, then both OTG2 and USB3 controllers will be used for that port. The OTG2 controller supports the
HS/FS/LS communication for backward compatibility and the USB3 controllers handle the SuperSpeed devices. When a new
device is connected, the USB3 controller will try to connect first. If that fails, it will hand-off the connection to the USB2 (OTG2)
controller. Hence, USB3 and OTG2 cannot be used concurrently for different purposes.
OTG2 can be used without USB3 when only USB2 connections are to be made. The USB3 controller remains unused in that case.
The connector type used depends on the functionality (host, peripheral, OTG) that is needed. If a Type-C connector is required,
external components are needed to handle the configuration channels.
See the NXP development platform schematic for an example USB Type-C implementation. See this useful link for additional USB
Type-C information.
3.12.1 USB routing recommendations
Use the following recommendations when routing USB signals:
• Route the DP/DM and SS_TX/SS_RX differential pairs first.
• Route the DP/DM and SS_TX/SS_RX signals on the top or bottom layer of the board if possible.
— Keep the DP/DM and SS_TX/SS_RX traces as short as possible.
— Route the DP/DM and SS_TX/SS_RX signals with a minimum number of corners. Use 45
o
turns instead of 90
o
turns.
— Minimize the layer changes (vias) on the DP/DM and SS_TX/SS_RX signals. Do not create stubs or branches.
• The trace width and spacing of the DP/DM and SS_TX/SS_RX signals should meet the differential impedance requirement
of 90 Ω.
• Route the traces over continuous planes (power or ground).
NXP Semiconductors
i.MX8 layout/routing recommendations
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
User's Guide 65 / 89
To Next Page
Loading...