Table 19. i.MX8 QXP DDR 17 x 17 mm package trace lengths/delays (continued)
Ball Name
Length
(microns)
XIM delay
(ps)
Ball Name
Length
(microns)
XIM delay (ps)
DDR_DCF19 6649.2 51.593 DDR_DQ12 6192.49 47.1092
DDR_DCF20 9160.92 69.4842 DDR_DQ13 8031.6 61.4137
DDR_DCF21 12748.4 93.2986 DDR_DQ14 6216.45 47.3891
DDR_DCF22 8400.13 64.0358 DDR_DQ15 6612.79 49.4634
DDR_DCF23 5342.64 41.9257 DDR_DQS0_N 9059.76 68.8765
DDR_DCF24 6846.35 53.3579 DDR_DQS0_P 9237.78 68.2606
DDR_DCF25 10998.4 82.0305 DDR_DQS1_N 6316.13 47.4771
DDR_DCF26 8592.59 65.9814 DDR_DQS1_P 6177.19 45.6418
DDR_DCF27 6287.16 48.9159 -
3.4.4 Length matching guides
The DDR Memory Controller and PHY used in the i.MX8QM and i.MX8QXP processors are capable of training out trace
mismatches between individual DQ and CA traces, but NXP continues to recommend designing PCB with length matching as
close as possible, because the training procedures are only able to align timing within a finite number of picoseconds. With good
trace matching techniques, it is possible to achieve a more accurate trace match than by relying on the automatic training routines
to match signal timing.
Length matching consists of taking all data or command/address traces in a group, making sure that the complete trace length of
each trace within that group is matched together and to the strobe/clock that latches those signals into the target device.
An example of a length match calculation of the control signals is shown in Table 20. This analysis was done for the LPDDR4-3200
implementation using the i.MX8 QM, but the mechanism would be the same for the LPDDR4-2400 (with relaxed timing due to the
1.2 GHz clock rate vs. 1.6 GHz clock rate). In this table, the “PCB Length” column was obtained from an Allegro PCB file, and the
“Pkg Length” column is the package conductor length, obtained from i.MX8 QM DDR package conductor lengths.
The “Via Length” column was obtained from the board stack-up, adding the total copper and dielectric thicknesses from Layer 1
down to layer 10, and adding this number twice as the net goes through two via transitions (L1 to L10, then back up to L1):
Total Length = PCB Length + Pkg Length + 2 x Via Length
The required matching is to the true clock signal within
+ 1 ps, which is approximately 6 mils. All nets are within this range
(1004.833 to 1016.833 mils). See i.MX8 QM LPDDR4-3200 routing recommendations and i.MX8 QXP LPDDR4-2400 routing
recommendations for examples of LPDDR4 routing.
Table 20. LPDDR4 length matching example (control signals)
Net Name
PCB Length Pkg Length Via
Length
Comment
DDR_CH0_CK0_P
586.13 324.067 50.318 Vias are L1-> L10->L1
1010.833 Total Net Length
Table continues on the next page...
NXP Semiconductors
i.MX8 layout/routing recommendations
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
User's Guide 30 / 89
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