NXP Semiconductors i.MX8 QM - i.MX8 QM;QXP Power Distribution Block Diagram

Table 31. i.MX8 maximum current design levels (continued)
Supply Input i.MX8 QM Max Current i.MX8 QXP Max Current
VDD_A72 5 A -----
VDD_A53 2.5 A -----
VDD_A35 ----- 2.5 A
VDD_DDR_CH0 2.5 A -----
VDD_DDR_CH1 2.5 A -----
VDD_DDR_VDDQ ----- 1.2 A
(2)
VDD_MEMC 2.5 A -----
1. There is only a single GPU power rail on the i.MX8 QXP
2. This does not include the current used by the external memory
3.10.1 i.MX8 QM/QXP power distribution block diagram
There are companion PMICs that provide a low-cost and efficient solution for powering the i.MX8 QM and i.MX8 QXP processors.
Figure 20 shows a block diagram of the power tree of the NXP i.MX8 QM development platform. It uses two PF8100 PMICs to
supply the power rails of the QM processor.
Figure 21 shows a block diagram of the power tree of the NXP i.MX8 QXP development platform. It uses a single PF8100 PMIC
to supply the power rails of the QXP processor.
NOTE: There are two companion power ICs that may be used (PF8100 and PF8200). These parts are substantially the same
(the PF8200 contains monitoring circuitry to support ASIL B safety level). Even though the NXP development platforms utilize the
PF8100, the PF8200 can be used in its place.
NXP Semiconductors
i.MX8 layout/routing recommendations
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
User's Guide 57 / 89