NXP Semiconductors i.MX8 QM - i.MX8 QM DDR Package Conductor Lengths

Table 16. DDR3L/LPDDR4 connectivity (continued)
Ball Name QXP Ball # QM Ball #
DDR3L
function (QXP)
LPDDR4 function
(QM, QXP)
DDR_DCF26 L7 AE47 AE7 A13 CA3_B
DDR_DCF27 K4 AE51 AE3 A10 CA0_B
DDR_DCF28 K6 AF50 AF4 CS_N[0] CS0_B
DDR_DCF29 K2 AE49 AE5 CS_N[1] CS1_B
DDR_DCF30 N7 AC53 AC1 CKE0 CKE0_B
DDR_DCF31 L5 AB52 AB2 CKE1 CKE1_B
DDR_DCF32 L3 AE53 AE1 A11 CA1_B
DDR_DCF33 P8 AF48 AF6 WE# CA2_B
3.4.2 i.MX8 QM DDR package conductor lengths
When performing the required trace length matching for LPDDR4 routing, the bond wires within the i.MX8 QM package must be
accounted for and included in the match calculation. The table below lists the lengths from each die I/O to the package ball, as
well as the propagation/fly time from the die I/O to the package ball.
Note: The values for substrate lengths and delay time are determined by the CAD program used to design the package substrate.
For simulation tools that use delay times as an input, the delay time numbers can be used, because they are more accurate.
The customer must ensure that the simulation tool is properly set up for using delay times. The package trace lengths provided
are exact, but no information is provided for the package substrate stack-up, so determining delay time directly from the trace
length can only be done as an approximation. NXP has determined that using trace lengths with Cadence Allegro provides more
consistent results.
Table 17. i.MX8 QM DDR 29 x 29 mm package trace lengths
Ball Name
Length
(microns)
XIM delay
(ps)
Ball Name
Length
(microns)
XIM delay (ps)
DDR_CH0_CK0_N 8252.205 70.4320 DDR_CH1_CK0_N 8252.205 71.2075
DDR_CH0_CK0_P 8231.301 70.4019 DDR_CH1_CK0_P 8231.301 70.3251
DDR_CH0_CK1_N 7122.412 63.2031 DDR_CH1_CK1_N 7122.422 63.7053
DDR_CH0_CK1_P 7116.659 62.7708 DDR_CH1_CK1_P 7116.659 62.8899
DDR_CH0_DCF00 5894.518 52.5252 DDR_CH1_DCF00 5896.059 53.0091
DDR_CH0_DCF01 5369.421 50.9911 DDR_CH1_DCF01 5365.999 50.7991
DDR_CH0_DCF02 6353.172 56.8037 DDR_CH1_DCF02 6353.172 57.0927
DDR_CH0_DCF03 4959.555 44.8336 DDR_CH1_DCF03 4959.555 45.5756
Table continues on the next page...
NXP Semiconductors
i.MX8 layout/routing recommendations
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
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