NXP Semiconductors i.MX8 QM - i.MX8 QXP Unused Input;Output Guidance

Table 36. i.MX8 QM unused signal strapping recommendations (continued)
Function Ball Name
Recommendation
if unused
MLB MLB_CLK_P/N, MLB_DATA_P/N, MLB_SIG_P/N 10 kΩ to ground
1
Common PCIe
interface balls
PCIE_REF_QR, PCIE_REXT,PCIE_PHY_PLL_REF_RETURN,
PCIE_SATA_REFCLK100M_P/N
Leave unconnected
2
DDR
DDR_CHx_DCFxx, DDR_CHx_CKx_P/N, DDR_CHx_DQxx, DDR_CHx_DMx,
DDR_CHx_DQSx_P/N
Leave unconnected
PCIe0 PCIE_TX0_P/N, PCIE_RX0_P/N Leave unconnected
PCIe1 PCIE1_TX0_P/N, PCIE1_RX0_P/N Leave unconnected
PCIe/SATA PCIE_SATA_TX0_P/N, PCIE_SATA_RX0_P/N Leave unconnected
SNVS/SCU
PMIC_EARLY_WARNING Leave unconnected
SNVS_TAMPER_IN[1:0], SNVS_TAMPER_OUT[1:0] 10 kΩ to ground
1
USB HSIC USB_HSIC0_DATA, USB_HSIC_STROBE Leave unconnected
USB_OTG1 USB_OTG1_DP/DN, USB_OTG1_ID Leave unconnected
3
USB_OTG2 USB_OTG2_DP/DN, USB_OTG2_ID, USB_OTG2_REXT 10 kΩ to ground
1,3
USB3
USB3_SS_REXT, USB_SS3_TX_P/N, USB_SS3_RX_P/N 10 kΩ to ground
1
USB3_SS_TCx Leave unconnected
1
– All balls can be connected and pulled down to ground as one group through one 10 kΩ resistor or as multiple groups
(according to the ball map location) through multiple 10 kΩ resistors.
2
– These balls must be properly designed/connected if any one of the three PCIe ports (PCIe0, PCIe1, and PCIe/SATA) is used.
3
– When the Serial Download Mode (SDP) is required, at least one OTG port must be connected. On entering the SDP mode,
the ROM code will poll both OTG ports until a connection is detected. The first port a connection is detected on is expected to
be the SDP port, at which point the other port will be ignored.
3.14.2 i.MX8 QXP unused input/output guidance
If a function on the i.MX8 QXP is not used, the I/Os and power rails of that function can be terminated to reduce overall board
power. See Table 37for the recommended connectivity for unused power supply rails and see Table 38 for the recommended
connectivity for unused signal contacts/interfaces.
NXP Semiconductors
i.MX8 layout/routing recommendations
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
User's Guide 71 / 89