Table 35. i.MX8 QM unused power rail strapping recommendations (continued)
Function Ball Name Recommendation if unused
VDD_FLEXCAN_1P8_3P3, VDD_MLB_DIG_1P8_3P3,
VDD_ADC_DIG_1P8, VDD_M4_GPT_UART_1P8_3P3,
VDD_PCIE_DIG_1P8, VDD_SIM0_1P8_3P3, VDD_HDMI_TX0_DIG_3P3
balls is prohibited when the
supply is not powered.
1
–
All balls can be connected and pulled down to ground as one group through one 10 kΩ resistor, or as multiple groups
(according to ball map location) through multiple 10 kΩ resistors. If the associated supply is not powered, the signal balls can
be left unconnected.
2
– These balls supply all three PCIe interfaces (PCIe0, PCIe1, and PCIe/SATA) and they must be properly connected/powered
if any one of the three PCIe ports is used.
3
–
The “USB Phys” designation includes all USB interfaces (USB_OTG1, USB_OTG2, and USB3). This power pin must be
properly connected/powered if any one of the three USB interfaces is used. VDD_USB_SS3_LDO_1P0_CAP must always be
powered, whether using an USB interface or not.
4
–
If the serial download mode is required, all USB OTG rails (1 and 2) MUST be powered, as per the data sheet operating
ranges table. In the serial download mode, both OTG ports are polled until activity is detected on one of the
ports. This process will fail if either OTG port is not powered correctly. Only if the serial download mode is never
required, either of the OTG supply rails can be considered unused.
5
–
If the MIPI DSI module is not used and the associated IO pins are used as GPIOs, the power rails must remain powered.
Table 36. i.MX8 QM unused signal strapping recommendations
Function Ball Name
Recommendation
if unused
ADC
ADC_IN[0:7] Leave unconnected
ADC_VREFH
Connect
to VDD_ADC_DIG_1P8
ADC_VREFL Ground
HDMI RX
HDMI_RX0_ARC_P/N, HDMI_RX0_CEC,
HDMI_RX0_HPD, HDMI_RX0_MON_5V
Leave unconnected
HDMI_RX0_CLK_P/N, HDMI_RX0_DATAx_P/N, HDMI_RX0_REXT Ground
HDMI_TX
HDMI_TX0_AUX_P/N, HDMI_TX0_CEC, HDMI_TX0_CLK_EDP3_P/N,
HDMI_TX0_DATAx_EDPx_P/N, HDMI_TX0_HPD
Leave unconnected
HDMI_TX0_REXT Ground
LVDS LVDSx_CHx_CLK_P/N, LVDS_CHx_TXx_P/N 10 kΩ to ground
1
MIPI-CSI MIPI_CSIx_CLK_P/N, MIPI_CSIx_DATAx_P/N 10 kΩ to ground
1
MIPI_DSI MIPI_DSIx_CLK_P/N, MIPI_DSIx_DATAx_P/N 10 kΩ to ground
1
Table continues on the next page...
NXP Semiconductors
i.MX8 layout/routing recommendations
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
User's Guide 70 / 89
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