input signal must be read by multiple software systems, then this signal must be connected to multiple GPIO inputs, each mapped
to different GPIO modules allocated to the said software systems.
Example mapping:
• SCU.GPIO0 for SCU
• LSIO.GPIO0 for M4_0
• LSIO.GPIO1 for M4_1
• LSIO.GPIO2 for secure AP
• LSIO.GPIO3-6 for non-secure AP
Similarly, I
2
C, SPI, and other interfaces that can be used to communicate to multiple devices must first be allocated to a software
system. Devices are then attached to interfaces owned by the software system that will use the device. This includes IOEXP
modules. These should be allocated to a software system and then connected to an interface allocated to the same software
system. The resets for the IOEXP must be connected to the GPIO or other IOEXP also owned by the same software system.
The board devices can only share a reset signal if the devices and the GPIO/IOEXP that drives the reset are owned by the same
software system.
The GPIO signals that are best associated with the SCU are especially critical. These GPIOs must be connected
to the SCU.GPIOn as accessing any of the LSIO. GPIOn requires much of the SoC fabric to be powered up, which
only happens late in the boot process.
NOTE
3.15.2 Planning for GPIO voltage supplies
The i.MX8 family of processors are designed to group GPIO pins with primary functions associated with a particular function into
an I/O power group necessary for that functionality. Examples include QSPI, UART, ESAI, EMMC, and USDHC. Changing the
logic voltage level of a particular function to meet interfaced components only requires changing the voltage supplied to an I/O
supply pin. The i.MX8 data sheets provide a detailed listing on the power group associated with the GPIO pins in the functional
contact assignments table.
If a particular functionality is not required in the custom design, the GPIO pins within that I/O power group become available for
other uses. Each pin is assigned an alternate functionality that can be found in the IOMUXD chapter of the reference manual and
it is cross-referenced in the reference manual chapter that describes the alternate functionality. Software drivers provided by NXP
can easily be reconfigured to use alternate pins for all functions listed as alternate uses for a pin. It is recommended to use a pin
with alternate functionality in preference to assigning a pin a general GPIO functionality. This requires the end user to modify the
software drivers to define explicitly how the pin should be used (bit-bang).
The voltage rail assigned to a particular I/O power group defines the logic level for all pins within that group. The designer should
try to group pins that require the same voltage logic level together on the same I/O power group. If a particular I/O power group
has no active pins assigned to it, then the design engineer can simply not connect the I/O power group pin for power saving.
For the maximum power saving, the design engineer can group the pins together in the same I/O power groups sorted by whether
the pins will be used only during periods of maximum functionality, low activity, or when in deep sleep (wake-up functions). In this
way, the design engineer can turn off the supply to the power rails at the board level when they are not needed.
3.15.3 Facilitating debug
The SCU is the system control unit. The boards designed for development should make the SCU UART TX output available
to users. The access to this UART port should only be eliminated on boards designed for final customer production, where all
software development (porting, testing, and so on) of the SCFW (System-Controller Firmware) was previously completed.
In addition, when using NXP’s DDR Stress test tool, it is recommended to make the SCU UART and the Application Processor (AP,
also known as the Cortex-A core) UART available. Furthermore, it is highly recommended to reuse the same AP UART port that
is used on NXP’s development boards. In these cases, UART0 is used (UART0_TX and UART0_RX). Choosing another UART
port may make the DDR Stress test tool unusable, because it relies on the proper UART0 port for communication with the user.
NXP Semiconductors
i.MX8 layout/routing recommendations
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
User's Guide 74 / 89
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