1. It is expected that the layout engineer and design team already have experience and training with DDR designs at
speeds of 933 MHz/1866 MT/s.
2. Use PCB materials with good dielectric constants (< 3.7 @ 5 GHz is desired). Some examples are Megtron6, Megtron4,
ThunderClad2, and MCL-HE-679G Type(S).
3. The 3W rule center to center is desired after the breakout, except for special declarations. The 2W rule is acceptable
for DDR3L ADD/CTRL/CMD signals for the strip line. 1W is defined as the dielectric distance between a trace and the
referenced GND plane.
4. The total number of vias should be two (or less) on each point-to-point single-ended/differential trace. An 18r10 imperial
via was simulated on the i.MX8 QXP development platform.
5. The DQS and DM with the same slice should have the same number of vias/layer changes.
6. Place at least one ground stitching via within 40 mils of the signal via when switching reference planes.
7. All length/delay matching calculations must take into account the PCB trace lengths plus the IC package delays.
8. Lengths of vias should also be taken into account when performing trace matching calculations.
9. It is suggested to incorporate the package trace lengths into the CAD tool’s constraint manager.
10. Bit swapping within each slice/byte lane is OK. Follow the custom bit swap done on NXP’s circuit boards to facilitate
easier/faster software support and bring-up.
11. All trace impedances are referenced to the associated ground plane. Only reference the ground planes when
determining impedance.
12. Referencing the 1.35 V power plane as the sole signal return path is not supported due to the dedicated package
design.
13. A full high-speed simulation of the DDR3L layout is required.
3.4.9 i.MX8 QXP DDR3L-1866 routing recommendations
Note: It is strongly recommended to adopt NXP layout if possible. The design files are available upon request.
The DDR3L-1866 must be routed with signal fly times matched, as shown in Table 24. Note that if the matched groups are not
all routed on the same layers with the same number of via transitions, then the trace length/delay of the via transitions must be
included in the overall calculation.
NXP recommends that users simulate their DDR3L implementation before fabricating PCBs.
Table 24. i.MX8 QXP DDR3L-1866 routing recommendations
DDR3L-1866 Fly-by
DDR3L Group
PCB and Package Prop Delay
Considerations
Min Max
CK_t/CK_c Clock As short as possible 1100 ps
Match the CK_t/CK_c within
2 ps for each DDR3L sub-
end. Incorporate package
lengths/delays into the
constraint manager.
Table continues on the next page...
NXP Semiconductors
i.MX8 layout/routing recommendations
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
User's Guide 40 / 89
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