1. VDD_LVDS0_1P0 – ball AV36
2. VDD_LVDS1_1P0 – ball AW35
3. VDD_MIPI_CSI0_1P0 – ball AV26
4. VDD_MIPI_CSI1_1P0 – ball AW25
5. VDD_MIPI_DSI0_1P0 – ball AU29
6. VDD_MIPI_DSI1_1P0 – ball AV28
7. VDD_MIPI_DSI0_PLL_1P0 – ball AW29
8. VDD_MIPI_DSI1_PLL_1P0 – ball AW27
The VDD_MAIN connectivity on the 12-layer development platform PCB is shown in Figure 28. In this figure, the purple is the
copper fill on the power plane layer PWR3 (layer 8) and the red is the etch on the top layer that provides connectivity from the
processor balls to the vias. The four vias providing the connectivity for the eight pins referenced above and the pins themselves
are highlighted in yellow.
Directly below these vias is a roughly U-shaped slot in the VDD_MAIN plane fill. The vias highlighted in green are the vias
that provide the connectivity to layer 8 for the VDD_MAIN balls AU35, AT30, and AT26 from left to right (VDD_MAIN_39:37,
respectively). Note that there is no physical connection across the slot between the VDD_MAIN pins and the VDD_LVDS/
VDD_MIPI pins, even though they are connected together on the schematic.
This slot forces the current flow for the remaining VDD_MAIN pins (and their return current) to go either to the right or left of this slot
and not through these pins/vias. This minimizes the noise on the LVDS/MIPI power inputs. It is recommended that i.MX8 users
implement this type of connectivity feature on their i.MX8 QM PCB designs.
Figure 28. VDD_MAIN connectivity (PWR3/layer 8)
3.12 USB connectivity
The i.MX8QM and i.MX8QXP both provide a USB2 port and a USB3 port. The USB3 port on i.MX8 QM/QXP consist of the SS
signal pairs (from the USB3 controller/PHY) plus the Dm/Dp signals from the OTG2 controller, as shown in Figure 29.
NXP Semiconductors
i.MX8 layout/routing recommendations
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
User's Guide 64 / 89
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