NXP Semiconductors i.MX8 QM - DRAM SI Simulation Guide

Figure 16. i.MX8 QXP development platform DDR3L routing (layer 12)
3.4.11 DRAM SI simulation guide
The simulation architecture includes the DDR controller (i.MX8 processor), the PCB, and the DDR device. The IBIS model
for the i.MX8 QM or i.MX8 QXP processors is available from NXP. The DRAM device IBIS model must be obtained from the
memory vendor.
The overview of how to check the SI performance of the DRAM layout is as follows:
Firstly, perform the S-parameter extraction:
• Requires a 2.5D full-wave extraction tool, such as Power-SI from Cadence.
NXP Semiconductors
i.MX8 layout/routing recommendations
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
User's Guide 48 / 89