Figure 17. Microstrip and strip line differential pair dimensions
Figure 18. Differential pair routing
3.8 Reset architecture/routing
A debounced reset button may be logically connected to the PMIC WDI pin for development purposes. By default, the PMIC WDI
will assert POR_B to the CPU and reset all voltages to their initial default power-on state. See Figure 19 for a diagram of the
recommended reset functionality.
Depressing push-button switch SW1 causes the supervisor IC at U5 to assert its RSTn output and drive POR_B_1V8 and
POR_RST_3V3_B low. This will also generate a Watchdog event to the PMIC. The RSTn will be released by the supervisor IC
approximately 210 ms after the push-button is released. However, the PMIC will then assert its POR_B output, which will keep
the POR_B_1V8 and POR_RST_3V3_B/SYS_RST_3V3_B & SYS_RST_1V8_B asserted until the PMIC supplies have reached
their operating voltages, at which time POR_B will be negated and the CPU may begin booting from reset.
NXP Semiconductors
i.MX8 layout/routing recommendations
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
User's Guide 52 / 89
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