Chapter 6
Using BSDL for board-level testing
The Boundary Scan Description Language (BSDL) is used for board-level testing after the components are assembled. The
interface for this test uses the JTAG pins. The definition is in IEEE Std 1149.1.
6.1 How BSDL works
A BSDL file defines the internal scan chain, which is the serial linkage of the IO cells, within a particular device. The scan chain
looks like a large shift register, which provides a means to read the logic level applied to a pin or to output a logic state on that
pin. Using JTAG commands, the test tool uses the BSDL file to control the scan chain so that the device-board connectivity can
be tested.
For example, when using an external ROM test interface, the test tool performs the following:
1. It outputs a specific set of addresses and controls to the pins connected to the ROM.
2. It performs a read command and scans out the values of the ROM data pins.
3. It compares the values read with the known golden values.
Based on this procedure, the tool determines whether the interface between the two parts is connected properly and does not
contain shorts or opens.
6.2 Boundary scan operation
NXP provides BSDL files for the i.MX8 QM and QXP processors to enable the boundary scan mode. To enter this mode, it
is required to set the needed COMPLIANCE_PATTERN. This pattern involves the TEST_MODE_SELECT and POR_B pins.
TEST_MODE_SELECT must be set to 0 and POR_B must be set to 1.
6.3 I/O pin power considerations
The boundary scan mode can set or read values from each of the available pins if the respective IO power supplies are active.
Note: The boundary scan mode was only tested at 1.8 V.
NXP Semiconductors
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
User's Guide 86 / 89
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