Table 24. i.MX8 QXP DDR3L-1866 routing recommendations (continued)
DDR3L-1866 Fly-by
DDR3L Group
PCB and Package Prop Delay
Considerations
Min Max
ADDR[15:0]
Address
Command Control
CK_t – 2 ps CK_t + 2 ps
Keep the maximum delay
skew of the ADD/CTL/CMD
bus within ±2 ps of
CK_t for each DDR3L sub-
end. Incorporate package
lengths/delays into the
constraint manager.
BA[2:0],CAS,RAS,WE
CKE,CS,RESET,ODT
DQ[7:0]
Byte 0 As short as possible 300 ps
Keep the maximum delay
skew of DQS/DQ/DMI within
±2 ps. Incorporate package
lengths/delays into the
constraint manager.
DMI0
DQS0_t/DQS0_c
DQ[15:8]
Byte 1 As short as possible 300 ps
DMI1
DQS1_t/DQS1_c
DQ[23:16]
Byte 2 As short as possible 300 psDMI2
DQS2_t/DQS2_c
DQ[31:24]
Byte 3 As short as possible 300 psDMI3
DQS3_t/DQS3_c
DQ[39:32]
Byte 4 (ECC) Short as possible 300 psDMI4
DQS4_t/DQS4_c
3.4.10 NXP i.MX8 QXP DDR3L-1866 validation board
The i.MX8 QXP DDR3L validation board used three 16-bit DDR3L devices in a fly-by topology: Two for the 32-bits of data and one
to support the ECC function. The i.MX8QXP board design differs from the previous fly-by topology boards in that two more series
resistors are added to each of the command/address traces. The first one is a 50 Ω resistor inserted in series with the nearest
DDR3L device and the second one is a 33 Ω resistor inserted in series with the middle DDR3L device. The details are as follows:
• 40 Ω single-ended trace impedance
1
is recommended for the trace up to the point where the trace branches to the nearest
DDR3L device. In addition, the trace branch connected to the termination resistor should also use 40 Ω single-ended line
NXP Semiconductors
i.MX8 layout/routing recommendations
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
User's Guide 41 / 89
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