Meeting the necessary timing requirements for a DDR memory system is highly dependent on the components chosen and
the design layout of the system as a whole. In this document, NXP cannot cover all the requirements needed to achieve a
design that meets full system performance over temperature, voltage, and part variation. The PCB trace routing, PCB dielectric
material, number of routing layers used, placement of bulk/decoupling capacitors on critical power rails, VIA placement, GND and
supply planes layout, and DDR controller/PHY register settings all are factors affecting the performance of the memory system.
Nevertheless, this hardware user’s guide contains a large amount of valuable design information that NXP believes aid the design
engineers in developing a DRAM memory system compliant with the JEDEC standards. NXP has validated design layouts for
information on how to properly design a PCB for best DDR performance. NXP strongly recommends duplicating an NXP validated
design as much as possible in the design of critical power rails, placement of bulk/decoupling capacitors, and DDR trace routing
between the processor and the selected DDR memory.
Processors that demonstrate full DDR performance on NXP validated designs, but do not function on customer designs, are not
considered marginal parts. A report detailing how the returned part behaved on an NXP validated system will be provided to the
customer as a closure to a customer-reported DDR issue. Customers bear the responsibility of properly designing the printed
circuit board, correctly simulating and modeling the designed DDR system, and validating the system under all expected operating
conditions (temperatures, voltages) before releasing their product to the market.
3.5 High-speed routing recommendations
For more information about general high-speed routing considerations, see
High-Frequency Design Considerations
(document AN12298).
The following list provides generic recommendations for routing traces for high-speed signals. Note that the propagation delay and
the impedance control should match to ensure the correct communication with the devices.
• High-speed signals (DDR, PCIe, RGMII, MIPI) must not cross gaps in the reference plane.
• Avoid creating slots, voids, and splits in reference planes. Review via placements to ensure that they do not inadvertently
create splits/voids (space vias out to eliminate this possibility).
• Ensure that ground stitching vias are present within 50 mils from signal layer transition vias on high-speed signals when
transitioning between different reference ground planes.
• A solid GND plane must be directly under crystals and the associated components and traces.
• Clocks or strobes that are on the same layer need at least 2.5x spacing from adjacent traces (2.5x height from the
reference plane) to reduce crosstalk.
• All synchronous interfaces should have appropriate bus length matching and relative clock length control.
For SD module interfaces:
• Match the data and CMD trace lengths (allowable delta depends on the access rate used).
• CLK should be longer than the longest signal in the Data/CMD group (+5 mils).
For the FlexSPI interface:
• Routing of the FlexSPI signals must follow the above rules, because the operating frequency of the interface can reach up
to 200 MHz with fast edges.
3.6 Disclaimers
Nothing in this document relieves the design engineer/customer from ultimate responsibility in producing a proper functioning
DRAM subsystem that meets JEDEC specifications.
It is expected that the design engineer already has a strong understanding of PCB design using high-speed components. This
is not an all-encompassing training document that can be used by beginning designers to produce reliable PCB designs using
modern processors.
Design engineers should use all available design guidelines provided by the manufacturers of other high-speed components
used in the system. Should a conflict arise between this document and the guidelines from other manufactures, contact NXP for
resolution (community.nxp.com).
NXP Semiconductors
i.MX8 layout/routing recommendations
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
User's Guide 50 / 89
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