Chapter 2
i.MX8 QM and QXP design checklist
This document provides a design checklist for the i.MX8 QM (29 x 29 mm package) and i.MX8 QXP (21 x 21 mm package)
processors. The design checklist tables contain recommendations for optimal design. Where appropriate, the checklist tables
also provide an explanation of the recommendation so that users have a greater understanding of why certain techniques are
recommended. All supplemental tables referenced by the checklist appear in sections following the design checklist tables.
2.1 Design checklist tables
Table 2. LPDDR4 recommendations (i.MX8 QM)
Checkbox Recommendation Explanation/Supplemental Recommendation
1. Connect the DDR_CHn_ZQ balls on the
processor (balls AF44 and AF10) to individual 240
Ω, 1 % resistors to GND.
This is a reference used during DRAM output buffer
driver calibration.
2. The ZQ0 and ZQ1 balls on each LPDDR4
device should be connected through 240 Ω, 1 %
resistors to the LPDDR4 VDD2 rail.
3. Place a 10 kΩ, 5 % resistor to the ground on
the DRAM reset signal.
This ensures adherence to the JEDEC specification until
the control is configured and starts driving the DDR.
4. The DDR_CHn_VREF balls on the processor
(balls U43 and U11) should be left unconnected.
The reference voltage generator is on the chip, so no
external source is required.
5. The QM balls DDR_CHn_DCF09 and
DDR_CHx_DCF25 should be left unconnected.
The ODT_CA balls on the LPDDR4 device should
be connected directly to the LPDDR4 VDD2 rail.
DDR_CH(0:1)_DCF09 = T52, T2 DDR_CH(0:1)_DCF25
= AF52, AF2 LPDDR4 ODT on the i.MX8 QM is
command-based, making the processor ODT_CA output
balls unnecessary.
6. The architecture for each chip inside the DRAM
package must be x16.
The processor does not support the byte mode specified
in JESD209-4C.
7. The processor balls DDR_CHn_ATO (balls
AF46/AF8), DDR_CHn_DTO0 (balls U45/U9), and
DDR_CHn_DTO1 (balls T44/T10) should be left
unconnected.
These are observability ports for manufacturing and they
are not used otherwise.
Table 3. LPDDR4 recommendations (i.MX8 QXP)
Checkbox Recommendation Explanation/Supplemental Recommendation
1. Connect the DDR_ZQ ball on the processor (ball
G9) to an external 240 Ω, 1 % resistor to GND.
This is a reference used during DRAM output buffer
driver calibration.
2. Connect the ZQ0/ZQ1 balls on the LPDDR4
device through 240 Ω, 1 % resistors to the VDD2
supply of the LPDDR4 device.
Table continues on the next page...
NXP Semiconductors
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
User's Guide 7 / 89
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