Table 3. LPDDR4 recommendations (i.MX8 QXP) (continued)
Checkbox Recommendation Explanation/Supplemental Recommendation
3. Place a 10 kΩ, 5 % resistor to the ground on the
DRAM reset signal.
This ensures the adherence to the JEDEC specification
until the control is configured and starts driving the DDR.
4. The DDR_VREF ball (AD8) should be left
unconnected.
The reference voltage generator is on the chip, so no
external source is required.
5. The QXP device balls DDR_DCF09 and
DDR_DCF25 should be left unconnected. The
ODT_CA balls on the LPDDR4 device should be
connected directly to the LPDDR4 VDD2 rail.
DDR_DCF09 = ball AB6, DDR_DCF25 = ball K8
The LPDDR4 ODT on the i.MX8 QXP is command-
based, making the processor ODT_CA output
balls unnecessary.
6. The architecture for each chip inside the DRAM
package must be x16.
The processor does not support the byte mode specified
in JESD209-4C.
7. The processor balls DDR_ATO (ball AB8) and
DDR_DTO0:1 (balls AC7, AE7) should be left
unconnected.
These are observability ports for manufacturing and they
are not used otherwise.
Table 4. I
2
C recommendations
Checkbox Recommendation Explanation/Supplemental Recommendation
1. Verify the target I
2
C interface clock rates.
The I
2
C bus can only be operated as fast as the slowest
peripheral on the bus. If faster operation is required, move the
slow devices to another I
2
C port.
2. Verify that there are no I
2
C address conflicts
on any of the I
2
C buses utilized.
There are multiple I
2
C ports available on the chip, so if
a conflict exists, move one of the conflicting devices to a
different I
2
C bus. If this is not possible, use a I
2
C bus switch
(NXP part number PCA9646).
3. Do not place more than one set of pull-up
resistors on the I
2
C lines.
This could result in excessive loading and potential incorrect
operation. Choose the pull-up value commensurate with the
bus speed being utilized.
4. Ensure that the VCC rail powering the i.MX8
I
2
C interface balls matches the supply voltage
used for the pull-up resistors and the slave I
2
C
devices.
Prevent device damage or incorrect operation due to
voltage mismatch.
Table 5. Debug recommendations – JTAG and UART
Checkbox Recommendation Explanation/Supplemental Recommendation
1. Do not use external pull-up or pull-down
resistors on JTAG_TDO.
JTAG_TDO is configured with an on-chip keeper circuit such
that the floating condition is actively eliminated if an external
pull resistor is not present.
Table continues on the next page...
NXP Semiconductors
i.MX8 QM and QXP design checklist
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
User's Guide 8 / 89
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