Table 5. Debug recommendations – JTAG and UART (continued)
Checkbox Recommendation Explanation/Supplemental Recommendation
2. Follow the recommendations for external pull-
up and pull-down resistors given in Table 15.
3. TEST_MODE_SELECT (ball BC49 on the
QM and ball AE29 on the QXP) should be
connected to the ground.
This ball is for factory use only.
Table 6. Reset and on/off recommendations
Checkbox Recommendation Explanation/Supplemental Recommendation
1. The POR_B input must be asserted at
powerup and remain asserted until the last
power rail for the devices required for system
boot is at its working voltage. This functionality
is controlled by the PMIC (PF8100, PF8200 or
PF7100).
A reset switch may be wired to the chip’s POR_B, which
is a cold-reset negative-logic input that resets all modules
and logic in the IC. POR_B may be used in addition to
internally generated power-on reset signal (logical AND,
both internal and external signals are considered active
low). While POR_B is asserted (low) on the i.MX8, output
PMIC_ON_REQ remains asserted (high).
2. For portable applications, the
ON_OFF_BUTTON input may be connected to
an ON/OFF SPST push-button switch to the
ground. On-chip debouncing is provided, and
this input has an on-chip pullup. If not used,
ON_OFF_BUTTON should be a no-connect.
A brief connection (0.5 sec < press < 4 sec) to GND in the OFF
mode causes the internal power management state machine
to change the state to ON. In the ON mode, a brief connection
to the GND generates an interrupt (intended to initiate
a software-controllable power-down). An approximately 5-
second (or more) connection to GND causes a forced OFF.
3. If PMIC_ON_REQ is not used, the pin
should be left unconnected.
-
Table 7. i.MX8 QM power/decoupling recommendations
Checkbox Recommendation Explanation/Supplemental Recommendation
1. Comply with the power-up sequence guidelines,
as described in the datasheet to guarantee reliable
operation of the device.
Any deviation from these sequences may result in the
following situations:
• Excessive current during the power-up phase.
• Prevention of the device from booting.
• Irreversible damage to the processor (worst case
scenario).
2. Maximum ripple voltage requirements.
A common requirement for the ripple noise should
be less than 5 % peak-to-peak of the supply voltage
nominal value.
3. The internal LDOs shown below should be
decoupled with individual pairs of 2.2 µF caps:
• VDD_HDMI_TX0_LDO_1P0_CAP
Place at least one capacitor underneath the BGA
package as close as possible to each LDO output
(desired trace length < 50 mils). The HDMI RX LDO
outputs should only be connected to the caps, while the
Table continues on the next page...
NXP Semiconductors
i.MX8 QM and QXP design checklist
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
User's Guide 9 / 89
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