NXP Semiconductors i.MX8 QM - Power Connectivity;Routing

Table 30. BRD_OSC_CAP_TRM_VALUE_24M
BRD_OSC_CAP_TRM_VALUE_24M[3..0] CL1 and CL2 capacitance
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010 (default)
1011
1100
1101
1110
1111
0 pF
2 pF
4 pF
6 pF
8 pF
10 pF
12 pF
14 pF
16 pF
18 pF
20 pF
22 pF
24 pF
26 pF
28 pF
30 pF
The 32K trim value is a signed offset from the default value of 16 pF, whereas the 24M trim value is an unsigned
offset starting from 0.
NOTE
The fuses can be programmed in a number of ways, for example with the SCU debug monitor commands
fuse.w fuse_row_index value and fuse.r fuse_row_index
or with the uboot commands fuse prog 0 fuse_row_index value
and fuse read 0 fuse_row_index.
3.10 Power connectivity/routing
Delivering clean and reliable power to the iMX8 QM and i.MX8 QXP internal power rails is critical to a successful board design.
The PCB PDN should be designed to accommodate the maximum output current from each SMPS into the i.MX8 supply balls.
See Table 31 for the design goals for each of the high-current i.MX8 QM and i.MX8 QXP power rails.
Table 31. i.MX8 maximum current design levels
Supply Input i.MX8 QM Max Current i.MX8 QXP Max Current
VDD_MAIN 5 A 5 A
VDD_GPU0
(1)
5 A 2.5 A
VDD_GPU1 5 A -----
Table continues on the next page...
NXP Semiconductors
i.MX8 layout/routing recommendations
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
User's Guide 56 / 89