NXP Semiconductors i.MX8 QM - Page 55

Table 28. Fuse row index 768 (continued)
Bits Description
29 BRD_OSC_32K_TRIM_VALID
0 – use 16 pF default value
1 – use TRIM_VALUE_32K
28..20 Reserved
19..16 BRD_OSC_CAP_TRM_VALUE_32K
See Table 28
15..4 Reserved
3..0 BRD_OSC_CAP_TRIM_VALUE_24M
See Table 29
Note 1: The fuse row index 768 is a one-time only programmable 32-bit word. Programming bit 30 to 1 may result in parts that are
unable to boot and they will have to be replaced.
Note 2: The trim values are listed per capacitor. For example, if the default value is set for BRD_OSC_CAP_TRM_VALUE_32K
(0000), CL1 = 16 pF, CL2 = 16 pF.
Table 29. BRD_OSC_CAP_TRM_VALUE_32K
BRD_OSC_CAP_TRM_VALUE_32K[19..16] CL1 and CL2 capacitance
1000
1001
1010
1011
1100
1101
1110
1111
0000 (default)
0001
0010
0011
0100
0101
0110
0111
0 pF
2 pF
4 pF
6 pF
8 pF
10 pF
12 pF
14 pF
16 pF
18 pF
20 pF
22 pF
24 pF
26 pF
28 pF
30 pF
NXP Semiconductors
i.MX8 layout/routing recommendations
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
User's Guide 55 / 89