Chapter 7
Revision history
Table 42. Revision History
REVISION DATE DESCRIPTION
0.0 6/9/2017 Draft version for initial review.
0.1 7/17/2017 Updated per comments from initial review. Began adding QXP information (WIP).
0.2 7/25/2017 Complete addition of QXP info. Distribute for review.
0.3 8/2/2017 Added comments from large group review.
0.4 8/7/2017 Added individual comments.
0.5 12/06/2018
Changes to Table 9 and Table 10, change to Table 26 single-ended trace impedance
recommendation, added i.MX8 QM PDN impedance target values to Table 32,
minor changes to paragraph Power routing/distribution requirements. Updated Table
31, Table 32, Table 33, and Table 34. Table 14 – added reference to 24 MHz
crystal tolerance table and added load capacitance. Table 13 – added HDMI CEC
recommendation. Table 5 – Added debug info. Table 12 – Add VBUS info. Table
31 and Table 33 – Added VBUS and updated ADC power info. Added Eye Diagram
widths for DDR Simulations. – Added 24 MHz tolerance requirements – Added layout
recommendations for 8QXP DDR3L. Added PDN numbers for MX8QM, updated
values for MX8QXP.- Added design DRAM jitter target requirements removed
from data sheet. -Added design disclaimers. – Added section for general GPIO
recommendations. – Added board stack up diagrams. -Added comment to simulation
section for 2T timing. – Updated recommendation for PCIE Ref CLK generator. -
Added comment for 24 MHz GND loop.
0.6
01/15/2019 Added fixes for USB implementation on B0 silicon.
1.0 01/2020 Updated Table 18 for QXP B0 DDR 21x21 mm package length.
2.3p 02/2021
- USB connectivity chapter rewritten.
- Updated 24 MHz crystal trimming considerations in Clock crystal
considerations chapter.
- VDD_ANA_1P8 (SCU_1V8) added into Table 41.
- Updated VDD_DDR_VDDQ max current guideline for 8QXP.
- Updated drive strength and ODT recommendations in the DRAM SI
Simulation Guide.
- Added considerations for PCIE_SATA0_PHY_PLL_REF_RETURN,
PCIE0_PHY_PLL_REF_RETURN, PCIE1_PHY_PLL_REF_RETURN (Table 11)
- Deleted 0.1uF capacitor requirement for VDD_GPU in Table 10.
- Updated the considerations for HDMI data and clock pull-down resistors in HDMI/
display port connectivity (i.MX8 QM)
Table continues on the next page...
NXP Semiconductors
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
User's Guide 87 / 89
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