the NXP development platforms is recommended. This is required also for the PCB connectivity associated with the
internal LDOs (VDD_xxx_CAP).
3. Optimize the static IR drop. This involves using very wide traces/plane fills to route high-current power nets and ensure
an adequate number of vias on the power net layer transitions. The neck down of fill areas and the current density
should be minimized. The maximum static IR drop on a board should be 1 % of the voltage rail (on a 1.1 V rail, the
maximum voltage drop should be 0.011 V).
4. AC resonance check – the target impedance at different frequencies should be near or below the specified values.
5. See Table 32 and Table 33 for the impedance targets vs. the frequency for the specified power rails for the i.MX8 QM
and i.MX8 QXP PCB designs, respectively.
Snapshots of the PDN breakout/routing for the i.MX8 QM development platform are included for illustrative purposes. Figure 22
shows the breakout of the high-current rails supplied by PMIC #1, while Figure 23 shows the breakout of the high-current rails
supplied by PMIC #2.
Figure 24, Figure 25, Figure 26, and Figure 27 show how each of these rails is connected to the i.MX8 QM. Note that many rails
are connected on multiple layers (VCC_CPU0/VCC_CPU1 on power layers 1 and 2, VCC_GPU0/VCC_GPU1 on layers 1 and 4,
and VDD_MEMC on power layers 2 and 4).
Table 32. i.MX8 QM PDN impedance targets
Supply Input < 20 MHz (max mΩ) 20 - ~ 100 MHz (max mΩ)
VDD_MAIN 20 mΩ 100 mΩ
VDD_GPU0 32 mΩ 160 mΩ
VDD_GPU1 32 mΩ 160 mΩ
VDD_A72 30 mΩ 150 mΩ
VDD_A53 50 mΩ 250 mΩ
VDD_DDR_CH0 30 mΩ 150 mΩ
VDD_DDR_CH1 30 mΩ 150 mΩ
VDD_MEMC 30 mΩ 150 mΩ
Table 33. i.MX8 QXP PDN impedance targets
Supply Input < 20 MHz (max mΩ) 20 - ~ 100 MHz (max mΩ)
VDD_MAIN 11 mΩ 50 mΩ
VDD_DDRIO 20 mΩ 84 mΩ
VDD_GPU_1P1 21 mΩ 107 mΩ
VDD_CPU_1P1 24 mΩ 133 mΩ
NXP Semiconductors
i.MX8 layout/routing recommendations
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
User's Guide 60 / 89
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