Table 38. i.MX8 QXP unused signal strapping recommendations
Function Ball Name Recommendation if unused
ADC
ADC_IN[0:5] Leave unconnected
ADC_VREFH
Connect
to VDD_ADC_DIG_1P8
ADC_VREFL Ground
DDR DDR_DCFxx, DDR_CKx_P/N, DDR_DQxx, DDR_DMx, DDR_DQSx_P/N Leave unconnected
3
Tamper/CSI
CSI_D[0:7], CSI_EN, CSI_HSYNC, CSI_MCLK, CSI_PCLK,
CSI_RESET, CSI_VSYNC
Leave unconnected
MIPI-CSI MIPI_CSI0_CLK_P/N, MIPI_CSI0_DATAx_P/N 10 kΩ to ground
1
MIPI_DSI MIPI_DSIx_CLK_P/N, MIPI_DSIx_DATAx_P/N 10 kΩ to ground
1
PCIe
PCIE_REF_QR, PCIE_REXT, PCIE_PHY_PLL_REF_RETURN, PCIE_
REFCLK100M_P/N, PCIE0_TX0_P/N, PCIE0_RX0_P/N
Leave unconnected
USB2_OTG1 USB_OTG1_DP/DN, USB_OTG1_ID Leave unconnected
2
USB2_OTG2 USB_OTG2_DP/DN, USB_OTG2_ID, USB_OTG2_REXT 10 kΩ to ground
1,2
USB3
USB3_SS_REXT, USB_SS3_TX_P/N, USB_SS3_RX_P/N 10 kΩ to ground
1
USB3_SS_TCx Leave unconnected
1
–
All balls can be connected and pulled down to ground as one group through one 10 kΩ resistor or as multiple groups
(according to the ball map location) through multiple 10 kΩ resistors.
2
–
When the Serial Download Mode (SDP) is required, at least one OTG port must be connected. On entering the SDP mode,
the ROM code will poll both OTG ports until a connection is detected. The first port a connection is detected on is expected to
be the SDP port, at which point the other port will be ignored.
3
-
The DDR pins that are not used by the technology chosen for the design (LPDDR4/DDR3L) should be left unconnected.
3.15 GPIO pin strategies
3.15.1 Allocating GPIOs
Many different software systems can be run on the same device. This includes multiple CPUs (Cortex-A, Cortex-M, DSP, and
so on) and security states (ATF, OP-TEE, OS, and so on). These different software systems must be usually isolated from each
other using available hardware like MMU, SMMU, XRDC2, XRDC, RDC, and so on. All of this isolation hardware protects on IP
boundaries or MMU pages (which is why the IP is mapped to separate pages). As a result, the allocation of the GPIO and other
interfaces is critical. Not allocating it correctly can result in a lack of isolation leading to safety/reliability issues that can only be
overcome with complex software such as virtual drivers.
The GPIO signals are grouped, 8 to 32 per the GPIO module. The SoC’s hardware responsible for providing isolation has access
controls on a per-module basis, not on a per-signal basis. As a result, the GPIO modules must first be allocated to software
systems. The GPIO signal usage must then be mapped to these modules, based on which software system has the access. If an
NXP Semiconductors
i.MX8 layout/routing recommendations
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
User's Guide 73 / 89
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