3.3.1 Stack-up recommendation (i.MX8 QM)
Due to the number of balls on the i.MX 8QM processor in the 29 mm x 29 mm package, it is recommended to use a minimum
12-layer PCB stack-up. Of the 12-layers on the PCB, a sufficient number of layers must be dedicated to power routing to ensure
the IR drop target of 1 % for the i.MX8 QM CPU power rails is met.
The constraints for the trace width depend on a number of factors, such as the board stack-up and associated dielectric and copper
thickness, required impedance, and required current (for power traces). The stack-up also determines the constraints for routing
and spacing. Consider the following when designing the stack-up and selecting board material:
• Board stack-up is critical for high-speed signal quality.
• Preplanning impedance of critical traces is required.
• High-speed signals must have reference planes on adjacent layers to minimize crosstalk.
• Use PCB materials that have good transmission qualities at high frequencies utilized by the i.MX8 QM interfaces. The
NXP i.MX8 QM customer platform utilizes Megtron 6.
Figure 1. i.MX8 QM board stack-up
3.3.2 Stack-up recommendation (i.MX8 QXP)
For the i.MX 8QXP processor in the 21 mm x 21 mm package, it is recommended to use a minimum 8-layer PCB stack-up. Of the
eight layers on the PCB, a sufficient number of layers must be dedicated to power routing to ensure that the IR drop target of 1 %
for the i.MX8 QXP CPU power rails is met. The Cu foil thickness of the power routing layers may be increased to provide additional
current carrying capacity.
Consider the following when designing the stack-up and selecting board material:
• Board stack-up is critical for high-speed signal quality.
NXP Semiconductors
i.MX8 layout/routing recommendations
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
User's Guide 20 / 89
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