NXP Semiconductors i.MX8 QM - LPDDR4-2400;3200 Design Recommendations

Table 21. LPDDR4 length matching example (byte lane 1 signals)
Net Name PCB Length Pkg Length Via Length Comment
DDR_CH0_DQS1_P
459.06 379.728 N/A Vias are L1->L3->L1
838.788 Total net length (mils)
DDR_CH0_DQS1_N
467.06 379.681 N/A Vias are L1->L3->L1
846.741 Total net length (mils)
DDR_CH0_DM1
607.66 235.725 N/A Vias are L1->L3->L1
843.385 Total net length (mils)
DDR_CH0_DQ8
538.45 296.925 N/A Vias are L1->L3->L1
835.375 Total net length (mils)
DDR_CH0_DQ9
504.71 330.115 N/A Vias are L1->L3->L1
834.825 Total net length (mils)
DDR_CH0_DQ10
514.51 323.706 N/A Vias are L1->L3->L1
838.216 Total net length (mils)
DDR_CH0_DQ11
480.39 355.539 N/A Vias are L1->L3->L1
835.929 Total net length (mils)
DDR_CH0_DQ12
630.51 204.330 N/A Vias are L1-L3->L1
834.840 Total net length (mils)
DDR_CH0_DQ13
551.58 283.834 N/A Vias are L1->L3->L1
835.414 Total net length (mils)
DDR_CH0_DQ14
544.91 290.237 N/A Vias are L1->L3->L1
835.147 Total net length (mils)
DDR_CH0_DQ15
581.26 255.423 N/A Vias are L1->L3->L1
836.683 Total net length (mils)
3.4.5 LPDDR4-2400/3200 design recommendations
The following list details generic guidelines that should be adhered to when implementing i.MX8 QM or i.MX8 QXP designs
using LPDDR4.
1. It is expected that the layout engineer and design team already have experience and training with DDR designs at
speeds of 1.6 GHz/3200 MT/s or 1.2 GHz/2400 MT/s).
NXP Semiconductors
i.MX8 layout/routing recommendations
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
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