NXP Semiconductors i.MX8 QM - Page 31

Table 20. LPDDR4 length matching example (control signals) (continued)
Net Name
PCB Length Pkg Length Via
Length
Comment
DDR_CH0_CK0_N
581.09 324.890 50.318 Vias are L1-> L10->L1
1006.616 Total net length (mils)
DDR_CH0_CA0_A
699.60 316.304 N/A DCF11 in package, L1 trace only
1015.904 Total net length (mils)
DDR_CH0_CA1_A
675.20 341.157 N/A DCF16 in package, L1 trace only
1016.357 Total net length (mils)
DDR_CH0_CA2_A
673.80 232.068 50.318 DCF00 in package, Vias are L1-> L10->L1
1006.504 Total net length (mils)
DDR_CH0_CA3_A
649.78 259.101 50.318 DCF08 in package, Vias are L1-> L10->L1
1009.517 Total net length (mils)
DDR_CH0_CA4_A
697.01 211.395 50.318 DCF01 in package, Vias are L1-> L10->L1
1009.041 Total net length (mils)
DDR_CH0_CA5_A
715.63 195.258 50.318 DCF03 in package, Vias are L1-> L10->L1
1011.524 Total net length (mils)
DDR_CH0_CS0_A
627.03 280.924 50.318 DCF10 in package, Vias are L1-> L10->L1
1007.960 Total net length (mils)
DDR_CH0_CKE0_A
537.29 369.077 50.318 DCF14 in package, Vias are L1-> L10->L1
1007.003 Total net length (mils)
DDR_CH0_CS1_A
649.06 264.731 50.318 DCF12 in package, Vias are L1-> L10->L1
1014.427 Total net length (mils)
DDR_CH0_CKE1_A
607.84 400.963 N/A DCF15 in package, L1 trace only
1008.803 Total net length (mils)
An example of the length match calculation of the byte lane 1 signals for the i.MX8 QM is shown in Table 21. In this table, the “PCB
Length” column was obtained from an Allegro PCB file and the “Pkg Length” column is the package conductor length obtained
from the i.MX8 QM DDR package conductor lengths.
The “Via Length” column is ignored for this match calculation, because all signals are routed on layer 3, which means that the via
lengths are equal and they cancel each other out.
NXP Semiconductors
i.MX8 layout/routing recommendations
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
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