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NXP Semiconductors PN544 C2 User Manual

NXP Semiconductors PN544 C2
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UM191812
PN544 C2 User Manual
Rev. 1.2 — 2010-06-16 User Manual
Document information
Info Content
Keywords PN544 C2, Logical Link Control Protocol, Host controller interface, Single
Wire Protocol, NFC 2
nd
generation, SIM centered solution, Powered by
the Field
Abstract This is a user manual for the PN544 C2 NFC IC.
The aim of the document is to describe the PN544 Firmware API enabling
you to design your NFC system.

Table of Contents

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NXP Semiconductors PN544 C2 Specifications

General IconGeneral
BrandNXP Semiconductors
ModelPN544 C2
CategoryControl Unit
LanguageEnglish

Summary

PN544 Software Architecture

System Overview

Provides a high-level view of the PN544's interface and software structure.

Host hardware interface configuration

SPI interface

Details the configuration of the PN544 as a slave SPI device, including clock phase and polarity.

I2C interface

Explains the PN544's role as an I2C slave and how to configure the interface and address.

ETSI Host Controller Interface Compliancy

ETSI HCI Commands/ Events Supported

Lists the ETSI HCI commands and events supported by the PN544, detailing their status.

ETSI HCI Registries Supported

Details the ETSI HCI registries supported by the PN544, categorized by function like Gate Administration and Identity Management.

NXP Host Controller Interface

Initialization & Default mode of PN544

Describes the PN544 setup at boot level, including gate and pipe creation for initialization.

System Management

Details the system management capabilities of PN544, including autonomous mode and self-tests.

Clock Management

SWP

Configuration of SWP link

Covers SWP link configuration, including enabling the link, request power pin, and baudrate.

Polling Loop

PollingLoop Management

Explains the Polling Loop concept as a sequence of phases, including reader and card emulation phases.

NXP_PL_RDPHASES parameter

Explains how to use the NXP_PL_RDPHASES registry to setup and launch the Polling Loop mechanism.

NXP_PL_EMULATION, NXP_PL_PAUSE parameters

Details NXP_PL_EMULATION and NXP_PL_PAUSE timings, defining emulation and pause modes.

NFC-WI

MIFARE PCD

NXP_MIFARE_RAW

Details the NXP_MIFARE_RAW command for exchanging raw data with MIFARE UltraLight cards.

NXP_MIFARE Commands and Registry

Explains NXP_MIFARE_CMD command for data exchange and its associated parameters and registry.

FeliCa Reader

Type F Reader RF gate

Covers the Type F Reader RF gate for FeliCa functionality and related proprietary commands.

NXP_FELICA_RAW Command

Details the NXP_FELICA_RAW command for raw data exchange with FeliCa cards.

NXP_FELICA_CMD Command

Explains the NXP_FELICA_CMD command for data exchange with FeliCa cards and its parameters.

Jewel/Topaz Reader

Jewel reader RF gate

Covers the Jewel reader RF gate for Jewel/Topaz functionality and proprietary commands.

NXP_JEWEL_RAW_CMD Command

Details the NXP_JEWEL_RAW_CMD command for using Jewel native commands in RAW format.

ISO15693

ISO15693 reader RF gate

Covers the ISO15693 reader RF gate for ISO15693 functionality and proprietary commands.

NXP_ISO15693_CMD Command

Explains the NXP_ISO15693_CMD command for accessing remote ISO15693 tags.

NFCIP-1

Initiator

Describes the NFCIP-1 Initiator role, including discovery, data exchange, and communication closure.

Target

Details the NFCIP-1 Target role, including activation, data exchange, and communication closure.

Reader RF gates – additional commands

Type A PICC

Type A PICC over NFC WI (SMX as a Type A card)

Explains Type A card emulation over NFC WI, referencing the secure element and NFC WI paragraph.

Type A PICC over SWP (UICC as a Type A card)

Describes Type A card emulation over SWP, referencing the UICC connection and SWP paragraph.

Type A PICC over host link (I2C, SPI, HSU) (host as a Type A card)

Details Type A card emulation over host links, including UID generation.

Type A PCD

Type A PCD over SWP (UICC as a Type A reader)

Explains how UICC acts as a Type A reader via SWP, referencing HCI specification and SWP paragraph.

Type A PCD over host link (I2C, SPI, HSU) (Host as a Type A reader)

Details how the host acts as a Type A reader via I2C, SPI, HSU, referencing HCI specification and Polling Loop.

Type B PICC

Type B PCD

GPIO(s)

Download

PN544 Configuration

PN544 register access

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