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NXP Semiconductors PN544 C2 User Manual
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UM191812
PN544 C2 User Manual
Rev. 1.2 — 2010-06-16
User Manual
Document infor
mation
Info
Content
Keywords
PN544 C2, Logical Link Cont
rol Protocol
, Host controller interface, Single
Wire Protocol, NFC 2
nd
generation, SIM centered solution, Powered by
the Field
Abstract
This is a user manual for the PN544 C2 NF
C IC.
The aim of the document is to descr
ibe the PN544 Firm
ware API enabling
you to design your NFC s
ystem.
2
Table of Contents
1 Introduction
3
2 Pn544 C2
3
3 Abbreviations
4
4 References
6
5 PN544 Software Architecture
7
System Overview
7
6 Host Hardware Interface Configuration
8
General Points
8
SPI Interface
10
C Interface
11
HSU Interface
12
7 NXP Logical Link Layer
12
Overview on Physical Interfaces
13
Link Layer Features
13
LLC on SWP
13
LLC on I C, SPI, UART
14
Frame Definition
14
Chaining Description
15
LLC Header Description
17
SHDLC Frame Types
17
Control Field
17
RSET Frame
19
Baud Rate Change (HSU)
21
CRC Description
23
Example
23
Error Detection and Error Handling
24
Inter-Frame-Character Timeout
24
Guard Host Timeout
25
Hsu
26
Example: Frame Transfer from Host to PN544
26
Example: Frame Transfer from PN544 to Host
26
Example: Full Duplex Transfer
27
I2C
28
Example: Communication from Master to Slave (Host to PN544)
28
Example: Communication from Slave to Master (PN544 to Host)
29
Spi
30
Example: Communication from Master to Slave (Host to PN544)
30
Communication from Slave to Master (PN544 to Host)
31
Duplex Communication
32
8 ETSI Host Controller Interface Compliancy
33
ETSI HCI Commands/ Events Supported
33
ETSI HCI Registries Supported
36
9 NXP Host Controller Interface
39
Access Rights NXP HCI Registry
39
Initialization & Default Mode of PN544
40
Gates & Pipes
40
Pipe ID Allocation
40
First Setup - Initialization Phase
40
After First Setup - Default State
44
System Management
45
Default Mode to Standby Mode
54
Host Link Wake-Up from Standby Mode
55
Information Notification
56
Default Secured Element in 'Power by the Field' Mode
56
Autonomous Mode
56
Clock Management
57
Clock Setup
57
Use of External Oscillator
57
Use of System Clock
58
Supported Clock Request/Acknowledge Setup.58
58
Clock Request Using GPIO Pin
59
Clock Request Using HCI Event
60
Clock Request & Release
60
No Clock Request
61
Request through CLKREQ Pin
61
Request through NXP_EVT_CLK_REQUEST
62
Event
62
Clock Acknowledge
63
Acknowledge with Timeout
63
Acknowledge through CLKACK Pin
64
Acknowledge through NXP_EVT_CLK_ACK
65
Event
65
CLK Request in NFC Active Target Mode
67
Swp
68
Configuration of SWP Link
71
Enabling SWP Link
71
Configuring Request Power Pin
71
Changing the Baudrate
71
Powering the UICC When Vbat < Vbat Critical
71
Managing UICC Rights in Card Emulation Mode and in Reader Mode
71
Reading SWP Status
72
Examples of Communication with the UICC Connected Via SWP
72
Card Emulation Use Case
72
Reader Use Case
74
UICC Dependency for PAYPASS Compliance
77
Polling Loop
78
Clock
81
Pollingloop Management
82
Detection Guard Time
83
Activation Timeout for NFC-IP1 Initiator
84
Activation Timeout for ISO14443-PICC & NFC-IP1 Target
84
NXP_PL_RDPHASES Parameter
85
Nxp_Pl_Emulation, Nxp_Pl_Pause
86
Parameters
86
Nxp_Evt_Activate_Rdphase
90
NXP_EVT_DEACTIVATE_RDPHASE Events
91
Example of Polling Loop
92
NFC-IP1 in Polling Loop
93
Multi Secure Element
93
RF Configuration
93
Card Emulation RF Step
93
Type B, 212Kbps and 424Kbps Passive Initiator and Active Initiator/Target
94
Nfc-Wi
95
Mifare Pcd
99
Nxp_Mifare_Raw
99
NXP_MIFARE Commands and Registry
100
Felica Reader
107
Jewel/Topaz Reader
110
Iso15693
113
Nfcip-1
115
Initiator
118
Target
125
Reader RF Gates - Additional Commands
129
Type a PICC
132
Type a PICC over NFC WI (SMX as a Type a Card)
132
Type a PICC over SWP (UICC as a Type a Card)
132
Type a PICC over Host Link (I2C, SPI, HSU) (Host as a Type a Card)
132
Multiple Type a PICC
132
Type a PCD
133
Type a PCD over SWP (UICC as a Type a Reader)
133
Type a PCD over Host Link (I2C, SPI, HSU) (Host as a Type a Reader)
133
Meaning of Additional Commands of Reader RF Gates for Type a
133
Several Type a Cards in the RF Field: Use NXP_WR_ACTIVATE_NEXT
133
Nxp_Wr_Activate_Id
133
Presence Check of ISO14443A Card: Use NXP_WR_PRESCHECK
136
Handling of Multiple Type a Readers
136
Type B PICC
139
Type B PICC over SWP (UICC as a Type B Card)
139
Type B PICC over Host Link (I2C, SPI, HSU) (Host as a Type B Card)
139
Multiple Type B PICC
139
Type B PCD
140
Type B PCD over SWP (UICC as a Type B Reader)
140
Type B PCD over Host Link (I2C, SPI, HSU) (Host as a Type B Reader)
140
Meaning of Additional Commands of Reader RF Gates for Type B
140
Several Type B Cards in the RF Field: Use NXP_WR_ACTIVATE_NEXT
140
Presence Check of ISO14443B Card: Use NXP_WR_PRESCHECK
140
Handling of Multiple Type B Readers
140
Gpio(S)
141
GPIO Direct Hardware Register Access
141
GPIO EEPROM Settings Access
141
Examples
141
Output Configuration
142
Read/Write an Output Pin
142
Input Configuration
143
Read an Input Pin (Write Is Not Possible)
143
Connect Internal Pull up or Pull down to the GPIO
143
Inverse Polarity
143
Download
144
Switch in 'Download' Mode
144
PN544 Debug Mode
146
SWP Digitized
146
PLL Lock & System Clock
146
RF Level Detector
147
RF Envelope TX
147
RF Signal RX
147
PN544 Configuration
149
SWP Configuration
149
SE Configuration
152
HW Configuration
153
RF Configuration
161
PN544 Register Access
162
GPIO Settings
162
10 Practical Approach on PN544 HCI
163
Reading PN544 Version Register
163
PN544 Software & Hardware Version
164
PN544 Versioning and Configuration Management
165
4
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NXP Semiconductors PN544 C2 Specifications
General
Brand
NXP Semiconductors
Model
PN544 C2
Category
Control Unit
Language
English
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