NXP Semiconductors
UM191812
PN544 C2 User Manual
191812 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User Manual Rev. 1.2 — 2010-06-16 30 of 172
Fig 23. I
2
C PN544 to Host Split Transfer
7.4.8 SPI
The PN544 performs its communication by using the signals NSS, MISO, MOSI, SCK.
PN544 only acts as slave; hence it only consumes but never drives the signals NSS,
MOSI and SCK. Only MISO is driven as output. The bit rate is given by the host.
Moreover an IRQ line needs to be connected which indicates pending data on the
PN544. The bits are conveyed using most significant bit, most significant byte first. The
interface can be used in full duplex mode.
These SPI relevant settings are read out during boot phase of the PN544. They are
coded by a hardware pin configuration (Refer to ‘Host hardware interface configuration
chapter’).
7.4.8.1 Example: Communication from Master to Slave (Host to PN544)
If the host wa
nts to write data, it will put NSS to low and will apply the clock on SCK and
puts the data on MOSI. Between every character, NSS is toggled. If there is no data
pending on PN544, the PN544 shall put 00h at MISO.
• If the LLC frame is longer than the length claims to be, the length field shall be taken
as reference.
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