NXP Semiconductors PN544 C2 - Overview on Physical Interfaces; Link Layer Features; LLC on SWP

NXP Semiconductors
UM191812
PN544 C2 User Manual
191812 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User Manual Rev. 1.2 — 2010-06-16 13 of 172
7.1 Overview on physical interfaces
Table 5. Physical host Interfaces Overview
I
2
C SPI HSU SWP
Communication
Flow
Half Duplex Full Duplex Full Duplex Full Duplex
Clock Generator Host Only Host Only Host and
Device
Device (CLF) Only
Speed Enforced by
host clock
Enforced by host
clock
Specified by
the host
Configurable by the
host.
Frame Start/ End
Condition
Guard times
2
Guard times Guard times As defined in SWP
(SOF, EOF)
Activation Host Host Host Device (CLF)
Bus Capabilities Yes Yes No No
Used Lines SDA, SCL,
IRQ
MOSI, MISO,
NSS, SCK, IRQ
RX, TX SWIO, VCC
The supported speeds of the interfaces are found in the PN544 Datasheet [7].
7.2 Link Layer Features
The link layer guarantees reliable data transfer and a balanced link over an unreliable
MAC layer. In order to guarantee reliability, the LLC layer is able to detect and able to
recover from erroneous situations.
The layer above (i.e. the HCI) can assume that all frames are delivered without errors
and in a sequential order.
7.3 LLC on SWP
The product will support all mandatory features as specified in the ETSI SWP
specification [2]. The optional features / parameters are as follows:
Default wi
ndow size is 4. The UICC may negotiate the window size down to 2.
SREJ is not supported
For more information, please refer to ETSI SWP specification [2].
2. Configurable, typically between 1ms and 100ms. . Currently disabled.