NXP Semiconductors PN544 C2 - HSU Interface; 7 NXP Logical Link Layer

NXP Semiconductors
UM191812
PN544 C2 User Manual
191812 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User Manual Rev. 1.2 — 2010-06-16 12 of 172
6.4 HSU interface
HSU interface default configuration is:
Data bit : 8 bits
Parity bit : none
Stop bit : 1 bit
Baud rate : 115200 bauds
Data order : LSB first
7. NXP Logical Link Layer
PN544 offers four interfaces using LLC on top of the physical layer. The logical link layer
of the SWP interface is according to the SWP specification (see [2]). The other interfaces
(i.e. I
2
C, SPI, and HSU) are derived from the SWP LLC layer to fit the needs of the
respective interface. We refer to the “NXP LLC” layer described in Fig 1 ‘System
Overview’.
1. Ho
st Interfaces
a. I
2
C
b. SPI
c. HSU (i.e. High Speed UART)
2. ETSI SWP Interface