NXP Semiconductors PN544 C2 - PollingLoop Management

NXP Semiconductors
UM191812
PN544 C2 User Manual
191812 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User Manual Rev. 1.2 — 2010-06-16 82 of 172
9.6.2 PollingLoop Management
At start up, the PN544 is in a “default” mode (The Power level of this mode is set
according to PWR_STATUS EEPROM area value). It waits for a command from the host,
or from an external reader if the RF level detector has been enabled (in that case Refer
to SWP & NFC-WI setup).
It stays infinitely in this state (until a command from the host is received).
The Polling Loop concept is a sequence of different phases: mainly Reader phases &
Card Emulation phases. The following figure shows a possible setup of PN544:
Type B
Emulation
Type F
@424
Type A
Reader Phase
Emulation Phase
Pause
NFC Active
Type F
@212
ISO15693
(1)
Fig 46. Polling Loop Overview