NXP Semiconductors PN544 C2 - HW configuration

NXP Semiconductors
UM191812
PN544 C2 User Manual
191812 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User Manual Rev. 1.2 — 2010-06-16 153 of 172
Address Name Comment Default
0x9B4B
NfcWi_SE_TimeOut_L
0x00
9.20.3 HW configuration
Table 133. HW configuration in EEPROM
Address Name Comment Default
0x9810
HW_Conf
TX-LDO configuration
-Bits 0-1 : TVDD Supply select for TX-LDO
00 ... 3.0 V
01 ... 3.0 V
10 ... 2.7 V
11 ... 3.3 V
-Bit 2 : Enables offset for TX-LDO, if set to 1
-Bit 3 : Power down TX-LDO in Card-emulation mode, if set to 1
-Bit 4 : RFU (keep unchanged)
-Bit 5 : Enable TX-LDO limiter, if set to 1
CLOCK configuration
-Bit 7 : 0 ... Use internal FracNPLL for clock generation
1 ... Use external crystal for clock generation
0xBC
0x9801
ANAIRQ_Conf
Analog-IRQ Configuration
-Bits 0-1 : RFU (keep unchanged)
-Bit 2 : Enable/Disable PMU-Vcc IRQ
-Bit 3 : RFU
-Bit 4 : Enable/Disable RF-Modulation Tuning
-Bit 5 : Enable/Disable SWP-Debug during boot-process
-Bits 6-7 : RFU
0x17
0x9F9D
TX_Current_Check
TX Overcurrent Protection
Set to 0x00 to disable the TX over current protection
0x02
0x9805
AST-TX1pass
Antenna Self Test: RFLD pass threshold on TX1 (1
st
parameter)
0x03
0x9806
AST-TX2pass
Antenna Self Test: RFLD pass threshold on TX2 (2
nd
parameter)
0x05
0x9807
AST-Current
Antenna Self Test: Current pass threshold (3
rd
parameter)
0x0E