NXP Semiconductors PN544 C2 - NXP_PL_RDPHASES parameter

NXP Semiconductors
UM191812
PN544 C2 User Manual
191812 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User Manual Rev. 1.2 — 2010-06-16 85 of 172
9.6.2.4 NXP_PL_RDPHASES parameter
To setu
p and launch the Polling Loop mechanism, the host has to use the
NXP_PL_RDPHASES registry. This registry allows choosing the desired type of
communication.
NXP_PL_RDPHASES registry contains:
• One bit that enables/disables the “Pause” mode (PN544 is in a non active state). To
enable the Card Emulation mode (i.e. the host or the UICC connected over SWP or a
SmartMX connected over NFC-WI, acting as a contactless card), the bit 7 of
NXP_PL_RDPHASES must be set to 0 (“Pause” disabled).
• Five bits that enable/disable the reader mode. There are different bits for the different
supported RF types:
− Detection type A: set to 1, this bit allows the host to behave as an ISO14443A
reader (ISO14443-4 or MIFARE or JEWEL) and as an NFC-IP1 Initiator.
− Detection type B: set to 1, this bit allows the host to behave as an ISO14443B
reader. The method used is the probabilistic approach.
− Detection type F 212/424: set to 1, these bits allow the host to behave as a FeliCa
reader and as an NFC-IP1 Initiator.
− Detection NFC Active: set to 1, this bit allows the host to behave as an NFC-IP1
Initiator in Active mode.
− Detection ISO15693: set to 1, this bit allows the host to behave as an ISO15693
reader.
NXP_PL_RDPHASES bits don’t start the desired mode. These are only “enable”.
NXP_PL_RDPHASES shall be used in addition to HCI commands (see following
examples).
The host must use NXP_PL_RDPHASES, to give itself the right to start reader and
emulation modes, and/or to control the UICC rights to behave as a reader.
Note:
The Polling sequence is always as follows: NFC Active, Type A reader, Type B
reader, FeliCa reader 424, FeliCa reader 212, ISO15693 reader and then Card
Emulation (or Pause). Of course, each phase can be disabled, but the sequence is
always the same.
Note:
NXP_PL_RDPHASES registry setup is lost after a Hardware reset (VEN Low) and
the default value of this registry is recovered.