NXP Semiconductors
UM191812
PN544 C2 User Manual
191812 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User Manual Rev. 1.2 — 2010-06-16 39 of 172
9. NXP Host Controller Interface
PN544 provides proprietary gates to enhance the HCI feature set given in [1] . Here is a
descri
ption of them. This is the block named “PN544 HCI” in “Fig 1 System Overview”.
9.1 Access Rights NXP HCI Registry
Explaining the NXP HCI is done in table format. One row lists the access rights of the
parameter. The first abbreviations are:
RO: Read Only (protection against writing)
RW: Read/ Write allowed
The second abbreviation given is the memory location to which the parameter is written.
REG: Register, volatile memory
Values are written to a memory which does not have any limitation with respect to write
cycles. It is valid until a power off/up sequence is performed or until Hardware Reset
(VEN pin use).
EEPROM: non volatile memory
Values written to this memory are stored in EEPROM area of the chip. Values are
persistent even if a reset or power down was performed. Please be aware that these
memory cells have a limit of ~100k write cycles. However, a true write cycle is performed
only when the value changes, so rewriting the same EEPROM stored registry value
multiple times does not affect the lifetime of the EEPROM.
RAM: volatile memory
Values written to this memory are persistent until a reset (VEN pin use) or power down is
seen. There are no limitations with respect to write cycles.
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