NXP Semiconductors
UM191812
PN544 C2 User Manual
191812 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User Manual Rev. 1.2 — 2010-06-16 162 of 172
9.21 PN544 register access
PN544 HW registers can be accessed using NXP_READ and NXP_WRITE commands.
9.21.1 GPIO settings
For a detailed description please refer to the ‘GPIO chapter’.
Table 135. GPIO register set
Address Name Comment
0xF820
PINV
Port Inversion register
Inverse the polarity
0xF821
PDIR
Port Direction Register
If set to 1, the corresponding GPIO is configured in output (whatever PEN value). If set to 0 and if
the corresponding PEN bit is set to 1, the corresponding GPIO is configured in input.
0xF822
DPUD
Pull Down Enable register
Set to 1, an internal pull down is connected to the corresponding GPIO.
0xF823
UPUD
Pull Up Enable Register
Set to 1, an internal pull up is connected to the corresponding GPIO.
0xF82A
PIN
Input Port Register
Read the input port value.
0xF82B
POUT
Output Port Register
Read or write the output port value.
0xF829
PEN
Signal Input Enable
If set to 1, and if the corresponding PDIR is set to 0, the corresponding GPIO is
configured in input
Note: Each bit in the configuration register represents the GPIO pin with the corresponding number
(i.e. bit0 = GPIO0)
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