NXP Semiconductors PN544 C2 - Polling Loop

NXP Semiconductors
UM191812
PN544 C2 User Manual
191812 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User Manual Rev. 1.2 — 2010-06-16 78 of 172
9.6 Polling Loop
The host could manage the polling loop mechanism through a dedicated gate
“PollingLoopMgt”.
Table 65. Polling Loop Management Gate
Gate G
ID
PollingLoopMgt gate ‘94’
Using this gate the host is able to:
- Configure the polling loop
- Manage clock request/acknowledge via host commands
- Receive information about UICC reader activities
Table 66. Polling Loop events
Value Event Description
‘01’ NXP_EVT_CLK_ACK This event is sent by the host to acknowledge the
clock request (if PlClockAck EEPROM area has
been previously set to 2)
‘02’ NXP_EVT_CLK_REQUEST This event is sent to the host to inform that the
input clock is requested (if PlClockRequest
EEPROM area has been previously set to 2)
‘03’ NXP_EVT_ACTIVATE_RDPHASE This event is sent to the host to inform that the SE
is requesting for the activation of the reader phases
in the polling loop (see NXP_PL_RDPHASES
registry entry).
‘04’ NXP_EVT_DEACTIVATE_RDPHASE This event is sent to the host to inform that the SE
is no more requesting for the activation of the
reader phases in the polling loop (see
NXP_PL_RDPHASES registry entry).
The NXP_EVT_CLK_REQUEST has one parameter:
Table 67. NXP_EVT_CLK_REQUEST parameter
Description Length
Status 1